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path:
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/
drivers
/
clk
/
renesas
/
r8a7795-cpg-mssr.c
Age
Commit message (
Expand
)
Author
Files
Lines
2021-10-15
clk: renesas: r8a779[56]x: Add MLP clocks
Andrey Gusakov
1
-0
/
+1
2021-03-12
clk: renesas: r8a7795: Add TMU clocks
Niklas Söderlund
1
-0
/
+6
2020-06-22
clk: renesas: rcar-gen3: Mark RWDT clocks as critical
Ulrich Hecht
1
-1
/
+1
2020-02-10
clk: renesas: r8a7795: Add RPC clocks
Dirk Behme
1
-0
/
+8
2019-06-18
clk: renesas: r8a7795: Add CMM clocks
Jacopo Mondi
1
-0
/
+4
2019-05-21
clk: renesas: r8a779{5|6|65}: Add TPU clock
Cao Van Dong
1
-0
/
+1
2019-04-02
clk: renesas: rcar-gen3: Rename DRIF clocks
Takeshi Kihara
1
-9
/
+9
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
Takeshi Kihara
1
-2
/
+2
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
Takeshi Kihara
1
-2
/
+2
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of HS-USB
Kazuya Mizuguchi
1
-2
/
+2
2019-04-02
clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
Kazuya Mizuguchi
1
-4
/
+4
2019-04-02
clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2
Simon Horman
1
-1
/
+1
2019-04-02
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
Simon Horman
1
-2
/
+2
2019-04-02
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
Takeshi Kihara
1
-2
/
+3
2018-12-04
clk: renesas: r8a7795: Add CPEX clock
Geert Uytterhoeven
1
-0
/
+1
2018-10-18
Merge branch 'clk-renesas' into clk-next
Stephen Boyd
1
-33
/
+34
2018-08-30
clk: renesas: use SPDX identifier for Renesas drivers
Wolfram Sang
1
-4
/
+1
2018-08-27
clk: renesas: r8a7795: Add OSC EXTAL predivider configuration
Geert Uytterhoeven
1
-33
/
+33
2018-08-27
clk: renesas: rcar-gen3: Rename rint to .r
Geert Uytterhoeven
1
-1
/
+2
2018-06-19
clk: renesas: r8a7795: Add CCREE clock
Gilad Ben-Yossef
1
-0
/
+1
2018-06-19
clk: renesas: r8a7795: Add CR clock
Geert Uytterhoeven
1
-0
/
+1
2018-02-12
clk: renesas: r8a7795: Add Z2 clock
Takeshi Kihara
1
-0
/
+1
2018-02-12
clk: renesas: r8a7795: Add Z clock
Takeshi Kihara
1
-0
/
+1
2017-10-16
clk: renesas: r8a7795: Correct parent clock of INTC-AP
Geert Uytterhoeven
1
-1
/
+2
2017-08-16
clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
Geert Uytterhoeven
1
-17
/
+17
2017-05-15
clk: renesas: r8a7795: Correct pwm, gpio, and i2c parent clocks on ES2.0
Geert Uytterhoeven
1
-13
/
+26
2017-05-15
clk: renesas: r8a7795: Add HS-USB ch3 clock
Takeshi Kihara
1
-0
/
+1
2017-05-15
clk: renesas: r8a7795: Add USB-DMAC ch3 clock
Takeshi Kihara
1
-0
/
+2
2017-05-15
clk: renesas: r8a7795: Add EHCI/OHCI ch3 clock
Takeshi Kihara
1
-0
/
+1
2017-03-30
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
Geert Uytterhoeven
1
-50
/
+151
2017-03-21
clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
Geert Uytterhoeven
1
-1
/
+1
2017-03-21
clk: renesas: r8a7795: Reformat core clock table
Geert Uytterhoeven
1
-10
/
+10
2017-03-21
clk: renesas: r8a7795: Correct name of watchdog clock
Geert Uytterhoeven
1
-1
/
+1
2017-03-21
clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs
Geert Uytterhoeven
1
-2
/
+2
2017-03-06
clk: renesas: r8a7795: Add IMR clocks
Sergei Shtylyov
1
-0
/
+4
2017-01-27
clk: renesas: r8a7795: Add IIC-DVFS clock
Keita Kobayashi
1
-0
/
+1
2016-11-07
clk: renesas: r8a7795: Fix HDMI parent clock
Takeshi Kihara
1
-1
/
+1
2016-11-02
clk: renesas: r8a7795: Obtain mode pin values from R-Car RST driver
Geert Uytterhoeven
1
-1
/
+7
2016-09-14
Merge tag 'clk-renesas-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/k...
Stephen Boyd
1
-0
/
+4
2016-09-12
clk: renesas: r8a7795: Add CMT clocks
Bui Duc Phuc
1
-0
/
+4
2016-08-11
clk: renesas: r8a7795: Fix SD clocks
Yoshihiro Shimoda
1
-4
/
+5
2016-06-21
clk: renesas: r8a7795: Add THS/TSC clock
Khiem Nguyen
1
-0
/
+1
2016-06-21
clk: renesas: r8a7795: Add DRIF clock
Ramesh Shanmugasundaram
1
-0
/
+8
2016-06-21
clk: renesas: r8a7795: Correct lvds clock parent
Geert Uytterhoeven
1
-1
/
+1
2016-06-21
clk: renesas: r8a7795: Provide FDP1 clocks
Kieran Bingham
1
-0
/
+3
2016-06-06
clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code
Geert Uytterhoeven
1
-355
/
+5
2016-04-26
clk: renesas: r8a7795: Add VIN clocks
Niklas Söderlund
1
-0
/
+8
2016-04-26
clk: renesas: r8a7795: Add CSI2 clocks
Niklas Söderlund
1
-0
/
+5
2016-04-06
clk: renesas: r8a7795: add RWDT clock
Wolfram Sang
1
-0
/
+1
2016-04-06
clk: renesas: r8a7795: add R clk
Wolfram Sang
1
-0
/
+16
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