diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-07-23 15:21:52 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-08-27 17:00:18 +0200 |
| commit | fdb78a8c35bce065272d71ac7eb64d6d7512db99 (patch) | |
| tree | a4c21684ffdaed69b2ff8791897bc8ace8fbd61e /drivers/clk/renesas/r8a7795-cpg-mssr.c | |
| parent | 5b394b2ddf0347bef56e50c69a58773c94343ff3 (diff) | |
| download | linux-fdb78a8c35bce065272d71ac7eb64d6d7512db99.tar.bz2 | |
clk: renesas: rcar-gen3: Rename rint to .r
All other internal clock names have a period prepended.
Hence rename the internal RCLK from "rint" to ".r", and move it to the
section where all other internal clocks are defined.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/clk/renesas/r8a7795-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a7795-cpg-mssr.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index a85dd50e8911..ccaea9e1849d 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -73,6 +73,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), + /* Core Clock Outputs */ DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), @@ -112,7 +114,6 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), - DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; |