diff options
| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2016-11-04 14:58:07 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-11-07 15:16:18 +0100 |
| commit | 0a30284b9fe19780d4587e74578e460469d88706 (patch) | |
| tree | a41ddd1e63cf6a68ee5202de5d61e1dae6445de8 /drivers/clk/renesas/r8a7795-cpg-mssr.c | |
| parent | e6e3558626f6dbc16bc13587a1a981dc2446300e (diff) | |
| download | linux-0a30284b9fe19780d4587e74578e460469d88706.tar.bz2 | |
clk: renesas: r8a7795: Fix HDMI parent clock
Correct HDMI parent clock so that the rate of the
HDMI clock is 1/4 rather than 1/2 of the rate of PLL1
as per the v0.52 (Jun, 15) manual.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a7795-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a7795-cpg-mssr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 726c3d7940b4..50698a7d9074 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -98,7 +98,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), - DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250), + DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), |