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path: root/drivers/clk/socfpga/clk-agilex.c
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2022-01-05clk: socfpga: agilex: Make use of the helper function ↵Cai Huoqing1-3/+1
devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Link: https://lore.kernel.org/r/20210907085137.4407-1-caihuoqing@baidu.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-09-24clk: socfpga: agilex: fix duplicate s2f_user0_clkDinh Nguyen1-9/+0
Remove the duplicate s2f_user0_clk and the unused s2f_usr0_mux define. Fixes: f817c132db67 ("clk: socfpga: agilex: fix up s2f_user0_clk representation") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210916225126.1427700-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-07-26clk: socfpga: agilex: add the bypass register for s2f_usr0 clockDinh Nguyen1-1/+1
Add the bypass register for the s2f_user0_clk. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Kris Chaplin <kris.chaplin@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210713144621.605140-3-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-07-26clk: socfpga: agilex: fix up s2f_user0_clk representationDinh Nguyen1-0/+9
Correct the s2f_user0_mux clock representation. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Kris Chaplin <kris.chaplin@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210713144621.605140-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-07-26clk: socfpga: agilex: fix the parents of the psi_ref_clkDinh Nguyen1-4/+4
The psi_ref_clk comes from the C2 node of the main_pll and periph_pll, not the C3. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Kris Chaplin <kris.chaplin@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210713144621.605140-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: agilex/stratix10: add support for the 2nd bypassDinh Nguyen1-1/+3
The EMAC clocks on Stratix10/Agilex/N5X have an additional bypass that was not being accounted for. The bypass selects between emaca_clk/emacb_clk and boot_clk. Because the bypass register offset is different between Stratix10 and Agilex/N5X, it's best to create a new function to calculate the bypass. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210611025201.118799-3-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: agilex/stratix10: fix bypass representationDinh Nguyen1-11/+46
Each of these clocks(s2f_usr0/1, sdmmc_clk, gpio_db, emac_ptp, emac0/1/2) have a bypass setting that can use the boot_clk. The previous representation was not correct. Fix the representation. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210611025201.118799-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: agilex/stratix10: remove noc_clkDinh Nguyen1-17/+15
Early documentation had a noc_clk, but in reality, it's just the noc_free_clk. Remove the noc_clk clock and just use the noc_free_clk. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210611025201.118799-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-03-30clk: socfpga: Fix code formattingStephen Boyd1-1/+2
This function's parameters are oddly formatted. Looks like a newline was missed or something. Fix it. Cc: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210331023119.3294893-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-03-30clk: socfpga: Convert to s10/agilex/n5x to use clk_hwDinh Nguyen1-54/+60
As recommended by Stephen Boyd, convert the Agilex/Stratix10/n5x clock driver to use the clk_hw registration method. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210302214151.1333447-3-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-12clk: socfpga: agilex: add clock driver for eASIC N5X platformDinh Nguyen1-2/+86
Add support for Intel's eASIC N5X platform. The clock manager driver for the N5X is very similar to the Agilex platform, we can re-use most of the Agilex clock driver. This patch makes the necessary changes for the driver to differentiate between the Agilex and the N5X platforms. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210212143059.478554-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: socfpga: agilex: Remove unused variable 'cntr_mux'YueHaibing1-13/+0
drivers/clk/socfpga/clk-agilex.c:24:37: warning: ‘cntr_mux’ defined but not used [-Wunused-const-variable=] static const struct clk_parent_data cntr_mux[] = { ^~~~~~~~ There is no caller in tree, so can remove it. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20200915020950.4688-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clkDinh Nguyen1-1/+1
Preliminary documentation documented the mpu_l2ram_clk, but since then, the mpu_l2ram_clk is no longer documented. It's now referred to as mpu_ccu_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20200616202417.14376-3-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19clk: socfpga: agilex: add nand_x_clk and nand_ecc_clkDinh Nguyen1-1/+5
And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main clock that is feeding the NAND IP and correct it's parent to be the l4_mp_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20200616202417.14376-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26clk: socfpga: agilex: add clock driver for the Agilex platformDinh Nguyen1-0/+454
For the most part the Agilex clock structure is very similar to Stratix10, so we re-use most of the Stratix10 clock driver. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lkml.kernel.org/r/20200512181647.5071-5-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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