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path: root/drivers/clk/meson/meson8b.h
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2020-07-21Merge branch 'clk-amlogic' into clk-nextStephen Boyd1-1/+3
2020-07-10Replace HTTP links with HTTPS ones: Common CLK frameworkAlexander A. Klimov1-1/+1
2020-07-09clk: meson: meson8b: add the vclk2_en gate clockMartin Blumenstingl1-1/+2
2020-07-09clk: meson: meson8b: add the vclk_en gate clockMartin Blumenstingl1-1/+2
2020-05-02clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl1-0/+4
2020-04-14clk: meson8b: export the HDMI system clockMartin Blumenstingl1-1/+0
2019-06-11clk: meson: meson8b: add the cts_i958 clockMartin Blumenstingl1-1/+1
2019-06-11clk: meson: meson8b: add the cts_mclk_i958 clocksMartin Blumenstingl1-1/+4
2019-06-11clk: meson: meson8b: add the cts_amclk clocksMartin Blumenstingl1-1/+4
2019-04-01clk: meson: meson8b: add the video decoder clock treesMartin Blumenstingl1-1/+16
2019-04-01clk: meson: meson8b: add the VPU clock treesMartin Blumenstingl1-1/+8
2019-04-01clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2Martin Blumenstingl1-1/+4
2019-02-13clk: meson: meson8b: fix the naming of the APB clocksMartin Blumenstingl1-1/+1
2019-01-07clk: meson: meson8b: add the GPU clock treeMartin Blumenstingl1-1/+8
2018-12-03clk: meson: meson8b: add the read-only video clock treesMartin Blumenstingl1-2/+51
2018-12-03clk: meson: meson8b: add the fractional divider for vid_pll_dcoMartin Blumenstingl1-0/+1
2018-11-23clk: meson: meson8b: add the CPU clock post divider clocksMartin Blumenstingl1-1/+12
2018-11-23clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3Martin Blumenstingl1-2/+2
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet1-1/+4
2018-05-18clk: meson: use SPDX license identifiers consistentlyJerome Brunet1-12/+1
2018-05-15clk: meson: meson8b: add support for the NAND clocksMartin Blumenstingl1-1/+4
2018-03-13clk: meson: add fdiv clock gatesJerome Brunet1-1/+6
2018-03-13clk: meson: add mpll pre-dividerJerome Brunet1-1/+2
2018-03-13clk: meson: rework meson8b cpu clockJerome Brunet1-1/+6
2018-03-13clk: meson: split divider and gate part of mpllJerome Brunet1-1/+5
2017-08-04clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl1-1/+8
2017-08-04clk: meson8b: expose every clock in the bindingsJerome Brunet1-99/+4
2017-06-12clk: meson8b: export the ethernet gate clockMartin Blumenstingl1-1/+1
2017-06-12clk: meson8b: export the USB clocksMartin Blumenstingl1-5/+5
2017-06-12clk: meson8b: export the gate clock for the HW random number generatorMartin Blumenstingl1-1/+1
2017-06-12clk: meson8b: export the SDIO clockMartin Blumenstingl1-1/+1
2017-06-12clk: meson8b: export the SAR ADC clocksMartin Blumenstingl1-2/+2
2017-03-27clk: meson8b: add the mplls clocks 0, 1 and 2Jerome Brunet1-1/+19
2016-09-01meson: clk: Add support for clock gatesAlexander Müller1-0/+5
2016-09-01clk: meson: Copy meson8b CLKID defines to private header fileAlexander Müller1-0/+107
2016-09-01meson: clk: Rename register names according to Amlogic datasheetAlexander Müller1-6/+5
2016-09-01meson: clk: Move register definitions to meson8b.hAlexander Müller1-0/+40