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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2019-05-20 22:03:18 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2019-06-11 11:02:04 +0200 |
| commit | c39c24c1cae2476629c83e63afb19c3ff8987abf (patch) | |
| tree | b02dabbfd780f00541eff1f5acda3ca804b27b0e /drivers/clk/meson/meson8b.h | |
| parent | f278f05e748cdce3d7994c5de7cc2f02cc185f65 (diff) | |
| download | linux-c39c24c1cae2476629c83e63afb19c3ff8987abf.tar.bz2 | |
clk: meson: meson8b: add the cts_mclk_i958 clocks
Add the SPDIF master clock also referred as cts_mclk_i958. The setup for
this clock is identical to GXBB, so this ports commit 3c277c247eabeb
("clk: meson: gxbb: add cts_mclk_i958") to the Meson8/Meson8b/Meson8m2
clock driver.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/meson8b.h')
| -rw-r--r-- | drivers/clk/meson/meson8b.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 03efa47e800f..c3787418088e 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -32,6 +32,7 @@ #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ #define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ +#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ #define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ @@ -174,8 +175,10 @@ #define CLKID_VDEC_HEVC_EN 205 #define CLKID_CTS_AMCLK_SEL 207 #define CLKID_CTS_AMCLK_DIV 208 +#define CLKID_CTS_MCLK_I958_SEL 210 +#define CLKID_CTS_MCLK_I958_DIV 211 -#define CLK_NR_CLKS 210 +#define CLK_NR_CLKS 213 /* * include the CLKID and RESETID that have |