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2020-08-08arm64: Fix __cpu_logical_map undefined issueKefeng Wang3-5/+16
2020-08-08arm64/fixmap: make notes of fixed_addresses more preciselyPingfan Liu1-4/+3
2020-07-31Merge branch 'for-next/read-barrier-depends' into for-next/coreCatalin Marinas14-74/+67
2020-07-31Merge branch 'for-next/tlbi' into for-next/coreCatalin Marinas11-17/+264
2020-07-31Merge branches 'for-next/misc', 'for-next/vmcoreinfo', 'for-next/cpufeature',...Catalin Marinas17-81/+469
2020-07-31arm64: use IRQ_STACK_SIZE instead of THREAD_SIZE for irq stackManinder Singh1-1/+1
2020-07-30arm64/mm: save memory access in check_and_switch_context() fast switch pathPingfan Liu2-8/+8
2020-07-30arm64: sigcontext.h: delete duplicated wordRandy Dunlap1-1/+1
2020-07-30arm64: ptrace.h: delete duplicated wordRandy Dunlap1-1/+1
2020-07-30arm64: pgtable-hwdef.h: delete duplicated wordsRandy Dunlap1-2/+2
2020-07-24arm64: enable time namespace supportAndrei Vagin1-0/+1
2020-07-24arm64/vdso: Restrict splitting VVAR VMAAndrei Vagin1-0/+13
2020-07-24arm64/vdso: Handle faults on timens pageAndrei Vagin1-4/+52
2020-07-24arm64/vdso: Add time namespace pageAndrei Vagin6-5/+46
2020-07-24arm64/vdso: Zap vvar pages when switching to a time namespaceAndrei Vagin1-0/+31
2020-07-24arm64/vdso: use the fault callback to map vvar pagesAndrei Vagin1-10/+15
2020-07-24arm64: Reserve HWCAP2_MTE as (1 << 18)Catalin Marinas3-0/+3
2020-07-23arm64/entry: deduplicate SW PAN entry/exit routinesArd Biesheuvel1-48/+47
2020-07-22arm64: s/AMEVTYPE/AMEVTYPERVladimir Murzin2-36/+36
2020-07-21arm64: perf: Expose some new events via sysfsShaokun Zhang2-0/+46
2020-07-21arm64: Reduce the number of header files pulled into vmlinux.lds.SWill Deacon6-7/+10
2020-07-21alpha: Replace smp_read_barrier_depends() usage with smp_[r]mb()Will Deacon2-13/+13
2020-07-21asm/rwonce: Don't pull <asm/barrier.h> into 'asm-generic/rwonce.h'Will Deacon4-0/+4
2020-07-21alpha: Override READ_ONCE() with barriered implementationWill Deacon2-54/+40
2020-07-20arm64: perf: Add cap_user_time_shortPeter Zijlstra1-5/+7
2020-07-20arm64: perf: Only advertise cap_user_time for arch_timerPeter Zijlstra1-6/+13
2020-07-20arm64: perf: Implement correct cap_user_timePeter Zijlstra1-9/+29
2020-07-20arm64: perf: Correct the event index in sysfsShaokun Zhang1-5/+8
2020-07-15arm64: tlb: Use the TLBI RANGE feature in arm64Zhenyu Ye2-29/+131
2020-07-15arm64: enable tlbi range instructionsZhenyu Ye2-0/+21
2020-07-15arm64: tlb: Detect the ARMv8.4 TLBI RANGE featureZhenyu Ye3-1/+15
2020-07-15arm64/hugetlb: Reserve CMA areas for gigantic pages on 16K and 64K configsAnshuman Khandual3-2/+42
2020-07-14arm64: stacktrace: Move export for save_stack_trace_tsk()Mark Brown1-1/+1
2020-07-14arm64/acpi: disallow writeable AML opregion mapping for EFI code regionsArd Biesheuvel1-0/+9
2020-07-14arm64/acpi: disallow AML memory opregions to access kernel memoryArd Biesheuvel2-14/+67
2020-07-10arm64: tlb: don't set the ttl value in flush_tlb_page_nosyncZhenyu Ye1-3/+2
2020-07-07arm64/cpufeature: Validate feature bits spacing in arm64_ftr_regs[]Anshuman Khandual1-3/+44
2020-07-07arm64: Shift the __tlbi_level() indentation leftCatalin Marinas1-22/+21
2020-07-07arm64: tlb: Set the TTL field in flush_*_tlb_rangeZhenyu Ye1-0/+10
2020-07-07arm64: tlb: Set the TTL field in flush_tlb_rangeZhenyu Ye2-7/+36
2020-07-07arm64: Add tlbi_user_level TLB invalidation helperZhenyu Ye1-6/+12
2020-07-07arm64: Add level-hinted TLB invalidation helperMarc Zyngier2-0/+54
2020-07-07arm64: Document SW reserved PTE/PMD bits in Stage-2 descriptorsMarc Zyngier1-0/+2
2020-07-07arm64: Detect the ARMv8.4 TTL featureMarc Zyngier3-1/+14
2020-07-03arm64/mm: Redefine CONT_{PTE, PMD}_SHIFTGavin Shan2-10/+10
2020-07-03arm64/defconfig: Enable CONFIG_KEXEC_FILEBhupesh Sharma1-0/+1
2020-07-03arm64/cpufeature: Replace all open bits shift encodings with macrosAnshuman Khandual2-26/+55
2020-07-03arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 registerAnshuman Khandual2-0/+14
2020-07-03arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 registerAnshuman Khandual2-0/+8
2020-07-03arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 registerAnshuman Khandual2-0/+6