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| author | Zhenyu Ye <yezhenyu2@huawei.com> | 2020-07-10 17:41:58 +0800 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2020-07-10 16:27:49 +0100 |
| commit | 61c11656b67b0a30f702f240aabe81fd93e702ac (patch) | |
| tree | 827c14c8caabbf4c8fb54982d9a23cd81aff96f3 /arch | |
| parent | 34e36d81a0ef76047fa12a0f8e0dce4369b435cf (diff) | |
| download | linux-61c11656b67b0a30f702f240aabe81fd93e702ac.tar.bz2 | |
arm64: tlb: don't set the ttl value in flush_tlb_page_nosync
flush_tlb_page_nosync() may be called from pmd level, so we
can not set the ttl = 3 here.
The callstack is as follows:
pmdp_set_access_flags
ptep_set_access_flags
flush_tlb_fix_spurious_fault
flush_tlb_page
flush_tlb_page_nosync
Fixes: e735b98a5fe0 ("arm64: Add tlbi_user_level TLB invalidation helper")
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
Link: https://lore.kernel.org/r/20200710094158.468-1-yezhenyu2@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/include/asm/tlbflush.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 39aed2efd21b..2cb275efcea3 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -209,9 +209,8 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma, unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); dsb(ishst); - /* This function is only called on a small page */ - __tlbi_level(vale1is, addr, 3); - __tlbi_user_level(vale1is, addr, 3); + __tlbi(vale1is, addr); + __tlbi_user(vale1is, addr); } static inline void flush_tlb_page(struct vm_area_struct *vma, |