Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2018-10-22 | RISC-V: Use Linux logical CPU number instead of hartid | Atish Patra | 1 | -9/+16 |
2018-10-22 | RISC-V: Use WRITE_ONCE instead of direct access | Atish Patra | 1 | -2/+3 |
2018-10-22 | RISC-V: Use mmgrab() | Palmer Dabbelt | 1 | -1/+2 |
2018-10-22 | RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu | Palmer Dabbelt | 1 | -4/+5 |
2018-10-22 | RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid | Palmer Dabbelt | 1 | -1/+1 |
2018-10-22 | RISC-V: Disable preemption before enabling interrupts | Atish Patra | 1 | -1/+5 |
2018-10-22 | RISC-V: Comment on the TLB flush in smp_callin() | Palmer Dabbelt | 1 | -0/+4 |
2018-08-13 | clocksource: new RISC-V SBI timer driver | Palmer Dabbelt | 1 | -1/+0 |
2017-09-26 | RISC-V: Init and Halt Code | Palmer Dabbelt | 1 | -0/+114 |