summaryrefslogtreecommitdiffstats
path: root/arch/riscv/kernel/smpboot.c
AgeCommit message (Expand)AuthorFilesLines
2023-01-25riscv: Move call to init_cpu_topology() to later initialization stageLey Foon Tan1-1/+2
2022-08-15riscv: topology: fix default topology reportingConor Dooley1-1/+2
2022-07-19riscv: cpu: Add 64bit hartid support on RV64Sunil V L1-4/+5
2022-05-11riscv: move boot alternatives to after fill_hwcapHeiko Stuebner1-2/+0
2022-05-11riscv: integrate alternatives better into the main architectureHeiko Stuebner1-2/+0
2022-01-20RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra1-1/+1
2021-05-12sched/core: Initialize the idle task with preemption disabledValentin Schneider1-1/+0
2021-04-26riscv: Introduce alternative mechanism to apply errata solutionVincent Chen1-0/+4
2021-01-14riscv: Add numa support for riscv64 platformAtish Patra1-1/+11
2020-08-20RISC-V: Remove CLINT related code from timer and archAnup Patel1-1/+0
2020-08-20RISC-V: Add mechanism to provide custom IPI operationsAnup Patel1-2/+1
2020-08-04RISC-V: Fix build warning for smpboot.cAtish Patra1-1/+1
2020-07-30RISC-V: Setup exception vector earlyAtish Patra1-1/+1
2020-07-30riscv: Fixup lockdep_assert_held with wrong param cpu_runningZong Li1-1/+0
2020-06-29RISC-V: Use a local variable instead of smp_processor_id()Greentime Hu1-3/+4
2020-03-31RISC-V: Add supported for ordered booting method using HSMAtish Patra1-1/+1
2020-03-31RISC-V: Add cpu_ops and modify default booting methodAtish Patra1-21/+30
2019-11-17riscv: provide native clint access for M-modeChristoph Hellwig1-0/+4
2019-10-28riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley1-1/+1
2019-10-28riscv: add missing header file includesPaul Walmsley1-0/+1
2019-10-28riscv: add prototypes for assembly language functions from head.SPaul Walmsley1-0/+2
2019-07-22RISC-V: Parse cpu topology during boot.Atish Patra1-0/+3
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-9/+1
2019-05-16RISC-V: Support nr_cpus command line option.Atish Patra1-1/+9
2019-04-30RISC-V: Implement nosmp commandline option.Atish Patra1-1/+11
2019-03-04RISC-V: Compare cpuid with NR_CPUS before mapping.Atish Patra1-0/+5
2019-03-04RISC-V: Do not wait indefinitely in __cpu_upAtish Patra1-3/+12
2019-02-11riscv: use for_each_of_cpu_node iteratorJohan Hovold1-2/+2
2019-01-23RISC-V: fix bad use of of_node_putAndreas Schwab1-5/+1
2018-12-21RISC-V: Fix of_node_* refcountAtish Patra1-1/+5
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra1-9/+16
2018-10-22RISC-V: Use WRITE_ONCE instead of direct accessAtish Patra1-2/+3
2018-10-22RISC-V: Use mmgrab()Palmer Dabbelt1-1/+2
2018-10-22RISC-V: Rename im_okay_therefore_i_am to found_boot_cpuPalmer Dabbelt1-4/+5
2018-10-22RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt1-1/+1
2018-10-22RISC-V: Disable preemption before enabling interruptsAtish Patra1-1/+5
2018-10-22RISC-V: Comment on the TLB flush in smp_callin()Palmer Dabbelt1-0/+4
2018-08-13clocksource: new RISC-V SBI timer driverPalmer Dabbelt1-1/+0
2017-09-26RISC-V: Init and Halt CodePalmer Dabbelt1-0/+114