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2020-03-16ARC: allow userspace DSP applications to use AGU extensionsEugeniy Paltsev1-0/+12
To be able to run DSP-enabled userspace applications with AGU (address generation unit) extensions we additionally need to save and restore following registers at context switch: * AGU_AP* * AGU_OS* * AGU_MOD* Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2020-03-16ARC: add support for DSP-enabled userspace applicationsEugeniy Paltsev1-0/+2
To be able to run DSP-enabled userspace applications we need to save and restore following DSP-related registers: At IRQ/exception entry/exit: * DSP_CTRL (save it and reset to value suitable for kernel) * ACC0_LO, ACC0_HI (we already save them as r58, r59 pair) At context switch: * ACC0_GLO, ACC0_GHI * DSP_BFLY0, DSP_FFT_CTRL Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2020-03-16ARC: handle DSP presence in HWEugeniy Paltsev1-0/+12
When DSP extensions are present, some of the regular integer instructions such as DIV, MACD etc are executed in the DSP unit with semantics alterable by flags in DSP_CTRL aux register. This register is writable by userspace and thus can potentially affect corresponding instructions in kernel code, intentionally or otherwise. So safegaurd kernel by effectively disabling DSP_CTRL upon bootup and every entry to kernel. Do note that for this config we simply zero out the DSP_CTRL reg assuming userspace doesn't really care about DSP. The next patch caters to the DSP aware userspace where this reg is saved/restored upon kernel entry/exit. Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2020-01-17ARCv2: fpu: preserve userspace fpu stateVineet Gupta1-0/+2
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-02-25ARC: boot log: cut down on verbosityVineet Gupta1-9/+0
The syscall ABI has long been fixed, so no need to call that out now. Also, there's no need to print really fine details such as norm, barrel-shifter etc. Those are given in a Linux enabled hardware config. So now we print just 1 line for all optional "instruction" related hardware features | | ISA Extn : atomic ll64 unalign mpy[opt 9] div_rem vs. 2 before | |ISA Extn : atomic ll64 unalign | : mpy[opt 9] div_rem norm barrel-shift swap minmax swape Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-02-25ARCv2: boot log: refurbish HS core/release identificationVineet Gupta1-1/+1
HS core names and releases have so far been identified based solely on IDENTIFY.ARCVER field. With the future HS releases this will not be sufficient as same ARCVER 0x54 could be an HS38 or HS48. So rewrite the code to use a new BCR to identify the cores properly. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-02-25ARCv2: Add explcit unaligned access support (and ability to disable too)Eugeniy Paltsev1-0/+1
As of today we enable unaligned access unconditionally on ARCv2. Do this under a Kconfig option to allow disable it for test, benchmarking etc. Also while at it - Select HAVE_EFFICIENT_UNALIGNED_ACCESS - Although gcc defaults to unaligned access (since GNU 2018.03), add the right toggles for enabling or disabling as appropriate - update bootlog to prints both HW feature status (exists, enabled/disabled) and SW status (used / not used). - wire up the relaxed memcpy for unaligned access Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com> [vgupta: squashed patches, handle gcc -mno-unaligned-access quick]
2019-02-21ARCv2: don't assume core 0x54 has dual issueVineet Gupta1-0/+8
The first release of core4 (0x54) was dual issue only (HS4x). Newer releases allow hardware to be configured as single issue (HS3x) or dual issue. Prevent accessing a HS4x only aux register in HS3x, which otherwise leads to illegal instruction exceptions Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-01-17ARC: boot log: print Action point detailsVineet Gupta1-1/+9
This now prints the number of action points {2,4,8} and {min,full} targets supported. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2019-01-17ARCv2: boot log: BPU return stack depthVineet Gupta1-1/+1
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-11-13ARCv2: boot log: updates for HS48: dual-issue, ECC, Loop BufferVineet Gupta1-1/+32
Print the hardware support for ECC, Loop Buffer as well as the runtime enabled status Note that unlike the existing boot printing, this one is not read from pre-decoded hardware capabilty info cached in cpuinfo[] struct. Instead we read the AUX regs on the spot and print it, without botherign to save anywhere. There is no point in saving static hardware capabilites in memory when its use is very sporadic and non-performance critical, mainly for /proc/cpuinfo. This gets worse in SMP, given it is per-cpu, and pretty much exactly same across all cpus. So only info needed at runtime (e.g. TLB geometry) needs to be cached in cpuinfo[]. So going fwd we will start converting code to this paradigm. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-10-03ARCv2: boot log: identify HS48 cores (dual issue)Vineet Gupta1-1/+2
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-10-03ARC: boot log: decontaminate ARCv2 ISA_CONFIG registerVineet Gupta1-4/+4
ARCv2 ISA_CONFIG and ARC700_BUILD build config registers are not compatible. cpuinfo_arc had isa info placeholder which was mashup of bits form both. Untangle this by defining it off of ARCv2 ISA info and it is fine even for ARC700 since former is a super set of latter (ARC700 buildonly has 2 bits for atomics and stack check). At runtime, we treat ARCv2 ISA info as a generic placeholder but populate it correctly depending on ARC700 or HS. This paves way for adding more HS specific bits in isa info which was colliding with the extra bits for arc700. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2017-02-06ARCv2: intc: Use ARC_REG_STATUS32 for addressing STATUS32 regYuriy Kolerov1-0/+3
It is better to use it instead of magic numbers. Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-12-19ARC: mm: No need to save cache version in @cpuinfoVineet Gupta1-1/+1
Historical MMU revisions have been paired with Cache revision updates which are captured in MMU and Cache Build Configuration Registers respectively. This was used in boot code to check for configurations mismatches, speically in simulations (such as running with non existent caches, non pairing MMU and Cache version etc). This can instead be inferred from other cache params such as line size. So remove @ver from post processed @cpuinfo which could be used later to save soem other interesting info. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-11-30ARC: breakout timer include code into separate header ...Vineet Gupta1-8/+1
... which allows for use in drivers/clocksource later Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-11-30ARC: breakout aux handling into a separate headerVineet Gupta1-84/+1
ARC timers use aux registers for programming and this paves way for moving ARC timer drivers into drivers/clocksource Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-11-07ARC: change return value of userspace cmpxchg assist syscallVineet Gupta1-0/+2
The original syscall only used to return errno to indicate if cmpxchg succeeded. It was not returning the "previous" value which typical cmpxchg callers are interested in to build their slowpaths or retry loops. Given user preemption in syscall return path etc, it is not wise to check this in userspace afterwards, but should be what kernel actually observed in the syscall. So change the syscall interface to always return the previous value and additionally set Z flag to indicate whether operation succeeded or not (just like ARM implementation when they used to have this syscall) The flag approach avoids having to put_user errno which is nice given the use case for this syscall cares mostly about the "previous" value. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-10-28ARC: boot log: refactor cpu name/release printingVineet Gupta1-1/+1
The motivation is to identify ARC750 vs. ARC770 (we currently print generic "ARC700"). A given ARC700 release could be 750 or 770, with same ARCNUM (or family identifier which is unfortunate). The existing arc_cpu_tbl[] kept a single concatenated string for core name and release which thus doesn't work for 750 vs. 770 identification. So split this into 2 tables, one with core names and other with release. And while we are at it, get rid of the range checking for family numbers. We just document the known to exist cores running Linux and ditch others. With this in place, we add detection of ARC750 which is - cores 0x33 and before - cores 0x34 and later with MMUv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-10-28ARC: boot log: don't assume SWAPE instruction supportVineet Gupta1-1/+1
This came to light when helping a customer with oldish ARC750 core who were getting instruction errors because of lack of SWAPE but boot log was incorrectly printing it as being present Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-10-28ARC: boot log: refactor printing abt features not captured in BCRsVineet Gupta1-0/+1
On older arc700 cores, some of the features configured were not present in Build config registers. To print about them at boot, we just use the Kconfig option i.e. whether linux is built to use them or not. So yes this seems bogus, but what else can be done. Moreover if linux is booting with these enabled, then the Kconfig info is a good indicator anyways. Over time these "hacks" accumulated in read_arc_build_cfg_regs() as well as arc_cpu_mumbojumbo(). so refactor and move all of those in a single place: read_arc_build_cfg_regs(). This causes some code redcution too: | bloat-o-meter2 arch/arc/kernel/setup.o.0 arch/arc/kernel/setup.o.1 | add/remove: 0/0 grow/shrink: 2/1 up/down: 64/-132 (-68) | function old new delta | setup_processor 610 670 +60 | cpuinfo_arc700 76 80 +4 | arc_cpu_mumbojumbo 752 620 -132 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-09-30ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 coresVineet Gupta1-9/+1
HS release 3.0 provides for even more flexibility in specifying the volatile address space for mapping peripherals. With HS 2.1 @start was made flexible / programmable - with HS 3.0 even @end can be setup (vs. fixed to 0xFFFF_FFFF before). So add code to reflect that and while at it remove an unused struct defintion Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-03-12ARC: build: Better way to detect ISA compatible toolchainVineet Gupta1-6/+0
ARC architecture has 2 instruction sets: ARCompact/ARCv2. While same gcc supports compiling for either (using appropriate toggles), we can't use the same toolchain to build kernel because libgcc needs to be unique and the toolchian (uClibc based) is not multilibed. uClibc toolchain is convenient since it allows all userspace and kernel to be built with a single install for an ISA. This however means 2 gnu installs (with same triplet prefix) are needed for building for 2 ISA and need to be in PATH. As developers we keep switching the builds, but would occassionally fail to update the PATH leading to usage of wrong tools. And this would only show up at the end of kernel build when linking incompatible libgcc. So the initial solution was to have gcc define a special preprocessor macro DEFAULT_CPU_xxx which is unique for default toolchain configuration. Claudiu proposed using grep for an existing preprocessor macro which is again uniquely defined per ISA. Cc: Michal Marek <mmarek@suse.cz> Suggested-by: Claudiu Zissulescu <claziss@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-02-18ARCv2: boot report CCMs (Closely Coupled Memories)Vineet Gupta1-12/+20
- ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2016-01-29ARC: shrink cpuinfo by not saving full timer BCRVineet Gupta1-2/+1
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: boot log: decode more mmu config itemsVineet Gupta1-1/+1
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: mm: compute TLB size as needed from ways * setsVineet Gupta1-2/+2
This frees up some bits to hold more high level info such as PAE being present, w/o increasing the size of already bloated cpuinfo struct Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: make write_aux_reg safer against macro substitutionVineet Gupta1-1/+1
It was generating warnings when called as write_aux_reg(x, paddr >> 32) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-08-20ARCv2: Support IO Coherency and permutations involving L1 and L2 cachesAlexey Brodkin1-0/+1
In case of ARCv2 CPU there're could be following configurations that affect cache handling for data exchanged with peripherals via DMA: [1] Only L1 cache exists [2] Both L1 and L2 exist, but no IO coherency unit [3] L1, L2 caches and IO coherency unit exist Current implementation takes care of [1] and [2]. Moreover support of [2] is implemented with run-time check for SLC existence which is not super optimal. This patch introduces support of [3] and rework of DMA ops usage. Instead of doing run-time check every time a particular DMA op is executed we'll have 3 different implementations of DMA ops and select appropriate one during init. As for IOC support for it we need: [a] Implement empty DMA ops because IOC takes care of cache coherency with DMAed data [b] Route dma_alloc_coherent() via dma_alloc_noncoherent() This is required to make IOC work in first place and also serves as optimization as LD/ST to coherent buffers can be srviced from caches w/o going all the way to memory Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> [vgupta: -Added some comments about IOC gains -Marked dma ops as static, -Massaged changelog a bit] Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-08-03ARCv2: Fix the peripheral address space detectionVineet Gupta1-4/+3
With HS 2.1 release, the peripheral space register no longer contains the uncached space specifics, causing the kernel to panic early on. So read the newer NON VOLATILE AUX register to get that info. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-22ARCv2: MMUv4: cache programming model changesVineet Gupta1-2/+3
Caveats about cache flush on ARCv2 based cores - dcache is PIPT so paddr is sufficient for cache maintenance ops (no need to setup PTAG reg - icache is still VIPT but only aliasing configs need PTAG setup So basically this is departure from MMU-v3 which always need vaddr in line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG, IC_PTAG respectively. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-22ARCv2: MMUv4: TLB programming Model changesVineet Gupta1-1/+1
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-22ARCv2: Support for ARCv2 ISA and HS38x coresVineet Gupta1-4/+49
The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-22ARCv2: [intc] HS38 core interrupt controllerVineet Gupta1-0/+1
Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-22ARC: uncached base is hard constant for ARC, don't save itVineet Gupta1-1/+0
ioremap already uses the hard define, just make sure BCR value matches that Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19ARC: entry.S: Introduce INTERRUPT_{PROLOGUE,EPILOGUE}Vineet Gupta1-3/+0
-common'ize macros for level 1 and level 2 interrupts Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-06-19ARC: compress cpuinfo_arc_mmu (mainly save page size in KB)Vineet Gupta1-1/+2
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-04-13ARC: Fix RTT boot printingVineet Gupta1-0/+1
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-04-13ARC: cosmetic: Remove unused ECR bitfield masksVineet Gupta1-6/+3
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-04-13ARC: Fix WRITE_BCRVineet Gupta1-2/+2
* There was obvious bit rot due to lack of use * Old naming was confusing since BCR are read only Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-10-13ARC: boot: cpu feature print enhancementsVineet Gupta1-24/+53
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-10-13ARC: unbork FPU save/restoreVineet Gupta1-8/+0
Fixes: 2ab402dfd65d15a4b2 "ARC: make start_thread() out-of-line" CC: <stable@vger.kernel.org> #3.16 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-10-13ARC: remove extraneous __KERNEL__ guardsVineet Gupta1-4/+0
Verified by doing make headers_install as none of these files are exported to userspace
2014-07-23ARC: cache boot reporting updatesVineet Gupta1-1/+1
* print aliasing or not, VIPT/PIPT etc * compress param storage using bitfields * more use of IS_ENABLED to de-uglify code Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-06-26ARC: pt_regs update #5: Use real ECR for pt_regs->event vs. synth valuesVineet Gupta1-0/+4
pt_regs->event was set with artificial values to identify the low level system event (syscall trap / breakpoint trap / exceptions / interrupts) With r8 saving out of the way, the full word can be used to save real ECR (Exception Cause Register) which helps idenify the event naturally, including additional info such as cause code, param. Only for Interrupts, where ECR is not applicable, do we resort to synthetic non ECR values. SAVE_ALL_TRAP/EXCEPTIONS can now be merged as they both use ECR with different runtime values. The ptrace helpers now use the sub-fields of ECR to distinguish the events (e.g. vector 0x25 is trap, param 0 is syscall...) The following benefits will follow: (1) This centralizes the location of where ECR is saved and will allow the cleanup of task->thread.cause_code ECR placeholder which is set in non-uniform way. Then ARC VM code can safely rely on it being there for purpose of finer grained VM_EXEC dcache flush (based on exec fault: I-TLB Miss) (2) Further, ECR being passed around from low level handlers as arg can be eliminated as it is part of standard reg-file in pt_regs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-06-22ARC: Entry Handler tweaks: Avoid hardcoded LIMMS for ECR valuesVineet Gupta1-0/+5
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-06-22ARC: cache detection code bitrotVineet Gupta1-1/+1
* Number of (i|d)cache ways can be retrieved from BCRs and hence no need to cross check with with built-in constants * Use of IS_ENABLED() to check for a Kconfig option * is_not_cache_aligned() not used anymore Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-06-22ARC: Disintegrate arcregs.hVineet Gupta1-116/+0
* Move the various sub-system defines/types into relevant files/functions (reduces compilation time) * move CPU specific stuff out of asm/tlb.h into asm/mmu.h Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-02-15ARC: Boot #2: Verbose Boot reporting / feature verificationVineet Gupta1-10/+112
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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