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| author | Faiz Abbas <faiz_abbas@ti.com> | 2019-04-01 18:28:04 +0530 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2019-04-15 11:55:54 +0200 |
| commit | e374e87538f4c7cd364bce6b9048ad5829ccc604 (patch) | |
| tree | a0004296e8224632bf68fc376b527b05ff9f980f /usr | |
| parent | 3b407b4f3a9273467a6b3d6a640948a739794950 (diff) | |
| download | linux-e374e87538f4c7cd364bce6b9048ad5829ccc604.tar.bz2 | |
mmc: sdhci_am654: Clear HISPD_ENA in some lower speed modes
According to the AM654x Data Manual[1], the setup timing in lower speed
modes can only be met if the controller uses a falling edge data launch.
To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be
cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25
speed modes.
Use the sdhci writeb callback to implement this condition.
[1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'usr')
0 files changed, 0 insertions, 0 deletions