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| author | James Morse <james.morse@arm.com> | 2022-11-30 17:16:13 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-12-01 15:53:14 +0000 |
| commit | d3e1aa85b1b27b0e6d6f8d8b0bf0a9a04ed1d40a (patch) | |
| tree | 13c7c552db7c79bc93b5ba31acbcda34292ff8f4 /arch/arm64/include/asm/sysreg.h | |
| parent | a3aab94801dee86cc9d7d43a611c71688a483908 (diff) | |
| download | linux-d3e1aa85b1b27b0e6d6f8d8b0bf0a9a04ed1d40a.tar.bz2 | |
arm64/sysreg: Standardise naming for MVFR1_EL1
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the MVFR1_EL1 register use lower-case for feature
names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-15-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 0d4ab1c78d22..5f2dfbc4a347 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -778,14 +778,14 @@ #define MVFR0_EL1_FPSP_SHIFT 4 #define MVFR0_EL1_SIMDReg_SHIFT 0 -#define MVFR1_SIMDFMAC_SHIFT 28 -#define MVFR1_FPHP_SHIFT 24 -#define MVFR1_SIMDHP_SHIFT 20 -#define MVFR1_SIMDSP_SHIFT 16 -#define MVFR1_SIMDINT_SHIFT 12 -#define MVFR1_SIMDLS_SHIFT 8 -#define MVFR1_FPDNAN_SHIFT 4 -#define MVFR1_FPFTZ_SHIFT 0 +#define MVFR1_EL1_SIMDFMAC_SHIFT 28 +#define MVFR1_EL1_FPHP_SHIFT 24 +#define MVFR1_EL1_SIMDHP_SHIFT 20 +#define MVFR1_EL1_SIMDSP_SHIFT 16 +#define MVFR1_EL1_SIMDInt_SHIFT 12 +#define MVFR1_EL1_SIMDLS_SHIFT 8 +#define MVFR1_EL1_FPDNaN_SHIFT 4 +#define MVFR1_EL1_FPFtZ_SHIFT 0 #define ID_PFR1_EL1_GIC_SHIFT 28 #define ID_PFR1_EL1_Virt_frac_SHIFT 24 |