diff options
| author | James Morse <james.morse@arm.com> | 2022-11-30 17:16:12 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-12-01 15:53:14 +0000 |
| commit | a3aab94801dee86cc9d7d43a611c71688a483908 (patch) | |
| tree | 75f4820705ee634808316e4b8ae2a913852ee3db /arch/arm64/include/asm/sysreg.h | |
| parent | d092106d73539905b5deadfa86be04ff141bcaa8 (diff) | |
| download | linux-a3aab94801dee86cc9d7d43a611c71688a483908.tar.bz2 | |
arm64/sysreg: Standardise naming for MVFR0_EL1
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the MVFR0_EL1 register use lower-case for feature
names where the arm-arm does the same.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-14-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 29d93a36eac9..0d4ab1c78d22 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -769,14 +769,14 @@ #define ID_PFR2_EL1_SSBS_SHIFT 4 #define ID_PFR2_EL1_CSV3_SHIFT 0 -#define MVFR0_FPROUND_SHIFT 28 -#define MVFR0_FPSHVEC_SHIFT 24 -#define MVFR0_FPSQRT_SHIFT 20 -#define MVFR0_FPDIVIDE_SHIFT 16 -#define MVFR0_FPTRAP_SHIFT 12 -#define MVFR0_FPDP_SHIFT 8 -#define MVFR0_FPSP_SHIFT 4 -#define MVFR0_SIMD_SHIFT 0 +#define MVFR0_EL1_FPRound_SHIFT 28 +#define MVFR0_EL1_FPShVec_SHIFT 24 +#define MVFR0_EL1_FPSqrt_SHIFT 20 +#define MVFR0_EL1_FPDivide_SHIFT 16 +#define MVFR0_EL1_FPTrap_SHIFT 12 +#define MVFR0_EL1_FPDP_SHIFT 8 +#define MVFR0_EL1_FPSP_SHIFT 4 +#define MVFR0_EL1_SIMDReg_SHIFT 0 #define MVFR1_SIMDFMAC_SHIFT 28 #define MVFR1_FPHP_SHIFT 24 |