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| author | Tony Lindgren <tony@atomide.com> | 2022-04-29 09:57:36 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2022-05-03 09:15:42 +0300 |
| commit | b0985e02787759d99a8e921215b6dee0a2980c8c (patch) | |
| tree | 474a8cc6afba93789be7ad8d70374d4e70eb4c8c /arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | |
| parent | 4e28ab96e311e4cf07f064f3bbe78e92ef013b15 (diff) | |
| download | linux-b0985e02787759d99a8e921215b6dee0a2980c8c.tar.bz2 | |
ARM: dts: Group omap3 CM_CLKSEL_CORE clocks
The clksel related registers on omap3 cause unique_unit_address and
node_name_chars_strict warnings with the W=1 or W=2 make flags enabled.
With the clock drivers updated, we can now avoid most of these warnings
by grouping the TI component clocks using the TI clksel binding, and
with the use of clock-output-names property to avoid non-standard node
names for the clocks.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index c74566ff1f22..c6ab51a36f39 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -20,13 +20,20 @@ }; }; - ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "ssi_ssr_div_fck_3430es2"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; }; ssi_ssr_fck: ssi_ssr_fck_3430es2 { |