ARM: dts: Group omap3 CM_CLKSEL_CORE clocks

The clksel related registers on omap3 cause unique_unit_address and
node_name_chars_strict warnings with the W=1 or W=2 make flags enabled.

With the clock drivers updated, we can now avoid most of these warnings
by grouping the TI component clocks using the TI clksel binding, and
with the use of clock-output-names property to avoid non-standard node
names for the clocks.

Signed-off-by: Tony Lindgren <tony@atomide.com>

3 files changed, 78 insertions, 56 deletions

diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
index 984e1385723e..7dbab6eb2e6d 100644
--- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -77,13 +77,30 @@
 		};
 	};
 
-	ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-divider-clock";
-		clocks = <&corex2_fck>;
-		ti,bit-shift = <8>;
-		reg = <0x0a40>;
-		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+	clock@a40 {
+		compatible = "ti,clksel";
+		reg = <0xa40>;
+		#clock-cells = <2>;
+		#address-cells = <0>;
+
+		ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {
+			#clock-cells = <0>;
+			compatible = "ti,composite-divider-clock";
+			clock-output-names = "ssi_ssr_div_fck_3430es1";
+			clocks = <&corex2_fck>;
+			ti,bit-shift = <8>;
+			ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+		};
+
+		usb_l4_div_ick: clock-usb-l4-div-ick {
+			#clock-cells = <0>;
+			compatible = "ti,composite-divider-clock";
+			clock-output-names = "usb_l4_div_ick";
+			clocks = <&l4_ick>;
+			ti,bit-shift = <4>;
+			ti,max-div = <1>;
+			ti,index-starts-at-one;
+		};
 	};
 
 	ssi_ssr_fck: ssi_ssr_fck_3430es1 {
@@ -147,16 +164,6 @@
 		clock-div = <1>;
 	};
 
-	usb_l4_div_ick: usb_l4_div_ick@a40 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-divider-clock";
-		clocks = <&l4_ick>;
-		ti,bit-shift = <4>;
-		ti,max-div = <1>;
-		reg = <0x0a40>;
-		ti,index-starts-at-one;
-	};
-
 	usb_l4_ick: usb_l4_ick {
 		#clock-cells = <0>;
 		compatible = "ti,composite-clock";
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
index c74566ff1f22..c6ab51a36f39 100644
--- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -20,13 +20,20 @@
 		};
 	};
 
-	ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-divider-clock";
-		clocks = <&corex2_fck>;
-		ti,bit-shift = <8>;
-		reg = <0x0a40>;
-		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+	clock@a40 {
+		compatible = "ti,clksel";
+		reg = <0xa40>;
+		#clock-cells = <2>;
+		#address-cells = <0>;
+
+		ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
+			#clock-cells = <0>;
+			compatible = "ti,composite-divider-clock";
+			clock-output-names = "ssi_ssr_div_fck_3430es2";
+			clocks = <&corex2_fck>;
+			ti,bit-shift = <8>;
+			ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+		};
 	};
 
 	ssi_ssr_fck: ssi_ssr_fck_3430es2 {
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 60e603127a0c..430dca208dc8 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -574,23 +574,47 @@
 		clock-div = <1>;
 	};
 
-	l3_ick: l3_ick@a40 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&core_ck>;
-		ti,max-div = <3>;
-		reg = <0x0a40>;
-		ti,index-starts-at-one;
-	};
+	/* CM_CLKSEL_CORE */
+	clock@a40 {
+		compatible = "ti,clksel";
+		reg = <0xa40>;
+		#clock-cells = <2>;
+		#address-cells = <0>;
 
-	l4_ick: l4_ick@a40 {
-		#clock-cells = <0>;
-		compatible = "ti,divider-clock";
-		clocks = <&l3_ick>;
-		ti,bit-shift = <2>;
-		ti,max-div = <3>;
-		reg = <0x0a40>;
-		ti,index-starts-at-one;
+		l3_ick: clock-l3-ick {
+			#clock-cells = <0>;
+			compatible = "ti,divider-clock";
+			clock-output-names = "l3_ick";
+			clocks = <&core_ck>;
+			ti,max-div = <3>;
+			ti,index-starts-at-one;
+		};
+
+		l4_ick: clock-l4-ick {
+			#clock-cells = <0>;
+			compatible = "ti,divider-clock";
+			clock-output-names = "l4_ick";
+			clocks = <&l3_ick>;
+			ti,bit-shift = <2>;
+			ti,max-div = <3>;
+			ti,index-starts-at-one;
+		};
+
+		gpt10_mux_fck: clock-gpt10-mux-fck {
+			#clock-cells = <0>;
+			compatible = "ti,composite-mux-clock";
+			clock-output-names = "gpt10_mux_fck";
+			clocks = <&omap_32k_fck>, <&sys_ck>;
+			ti,bit-shift = <6>;
+		};
+
+		gpt11_mux_fck: clock-gpt11-mux-fck {
+			#clock-cells = <0>;
+			compatible = "ti,composite-mux-clock";
+			clock-output-names = "gpt11_mux_fck";
+			clocks = <&omap_32k_fck>, <&sys_ck>;
+			ti,bit-shift = <7>;
+		};
 	};
 
 	rm_ick: rm_ick@c40 {
@@ -739,28 +763,12 @@
 		};
 	};
 
-	gpt10_mux_fck: gpt10_mux_fck@a40 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-mux-clock";
-		clocks = <&omap_32k_fck>, <&sys_ck>;
-		ti,bit-shift = <6>;
-		reg = <0x0a40>;
-	};
-
 	gpt10_fck: gpt10_fck {
 		#clock-cells = <0>;
 		compatible = "ti,composite-clock";
 		clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
 	};
 
-	gpt11_mux_fck: gpt11_mux_fck@a40 {
-		#clock-cells = <0>;
-		compatible = "ti,composite-mux-clock";
-		clocks = <&omap_32k_fck>, <&sys_ck>;
-		ti,bit-shift = <7>;
-		reg = <0x0a40>;
-	};
-
 	gpt11_fck: gpt11_fck {
 		#clock-cells = <0>;
 		compatible = "ti,composite-clock";