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author | Olga Kitaina <okitain@gmail.com> | 2022-06-28 21:18:24 +0530 |
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committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2022-06-29 13:38:08 +0200 |
commit | e16eceea863b417fd328588b1be1a79de0bc937f (patch) | |
tree | 3f5daf164c4ea3e3dc7e54158159b38a887a4cf5 /Documentation | |
parent | 7499bfeedb47efc1ee4dc793b92c610d46e6d6a6 (diff) | |
download | linux-e16eceea863b417fd328588b1be1a79de0bc937f.tar.bz2 |
mtd: rawnand: arasan: Fix clock rate in NV-DDR
According to the Arasan NAND controller spec, the flash clock rate for SDR
must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the
CLK line for the mode. The driver previously always set 100 MHz for NV-DDR,
which would result in incorrect behavior for NV-DDR modes 0-4.
The appropriate clock rate can be calculated from the NV-DDR timing
parameters as 1/tCK, or for rates measured in picoseconds,
10^12 / nand_nvddr_timings->tCK_min.
Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
CC: stable@vger.kernel.org # 5.8+
Signed-off-by: Olga Kitaina <okitain@gmail.com>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20220628154824.12222-3-amit.kumar-mahapatra@xilinx.com
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions