diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2019-02-06 11:32:37 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-02-07 16:51:12 +0100 |
| commit | 72acaa1343ea2c5c401649e39c21ed83192f8cf3 (patch) | |
| tree | 4748c11e9b15519eaf4fd3dba5bd8bc6247cf909 | |
| parent | 6fa39a5405db9a2e8621b49fd2d46fd585225853 (diff) | |
| download | linux-72acaa1343ea2c5c401649e39c21ed83192f8cf3.tar.bz2 | |
ARM: dts: sun9i: Add A80 GMAC RGMII pinmux setting
The GMAC (gigabit ethernet controller) supports RGMII to connect to
the ethernet PHY, for gigabit network speeds.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| -rw-r--r-- | arch/arm/boot/dts/sun9i-a80.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index f0c7acf2d0a4..6fb292e0b662 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -1000,6 +1000,19 @@ #size-cells = <0>; #gpio-cells = <3>; + gmac_rgmii_pins: gmac-rgmii-pins { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA7", "PA8", + "PA9", "PA10", "PA12", "PA13", + "PA15", "PA16", "PA17"; + allwinner,function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + i2c3_pins: i2c3-pins { pins = "PG10", "PG11"; function = "i2c3"; |