summaryrefslogtreecommitdiffstats
path: root/tools/perf/pmu-events/arch/x86/skylake/memory.json
blob: 3bd8b712c889d53c3e8557d67751a396849e1021 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
[
    {
        "PublicDescription": "Number of times a TSX line had a cache conflict.",
        "EventCode": "0x54",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "TX_MEM.ABORT_CONFLICT",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x54",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "TX_MEM.ABORT_CAPACITY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
        "EventCode": "0x54",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
        "EventCode": "0x54",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
        "EventCode": "0x54",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
        "EventCode": "0x54",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times we could not allocate Lock Buffer.",
        "EventCode": "0x54",
        "Counter": "0,1,2,3",
        "UMask": "0x40",
        "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x5d",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "TX_EXEC.MISC1",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
        "EventCode": "0x5d",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "TX_EXEC.MISC2",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
        "EventCode": "0x5d",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "TX_EXEC.MISC3",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "RTM region detected inside HLE.",
        "EventCode": "0x5d",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "TX_EXEC.MISC4",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
        "EventCode": "0x5d",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "TX_EXEC.MISC5",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
        "CounterMask": "6",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA3",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
        "CounterMask": "2",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xA3",
        "Counter": "0,1,2,3",
        "UMask": "0x6",
        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
        "CounterMask": "6",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Demand Data Read requests who miss L3 cache.",
        "EventCode": "0xB0",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
        "SampleAfterValue": "100003",
        "BriefDescription": "Demand Data Read requests who miss L3 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.",
        "EventCode": "0xC3",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "Errata": "SKL089",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
        "EventCode": "0xC8",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "HLE_RETIRED.START",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an HLE execution started.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times HLE commit succeeded.",
        "EventCode": "0xC8",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "HLE_RETIRED.COMMIT",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an HLE execution successfully committed",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Number of times HLE abort was triggered. (PEBS)",
        "EventCode": "0xC8",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "HLE_RETIRED.ABORTED",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "HLE_RETIRED.ABORTED_MEM",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "HLE_RETIRED.ABORTED_TIMER",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
        "EventCode": "0xC8",
        "Counter": "0,1,2,3",
        "UMask": "0x40",
        "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC8",
        "Counter": "0,1,2,3",
        "UMask": "0x80",
        "EventName": "HLE_RETIRED.ABORTED_EVENTS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
        "EventCode": "0xC9",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "RTM_RETIRED.START",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an RTM execution started.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times RTM commit succeeded.",
        "EventCode": "0xC9",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "RTM_RETIRED.COMMIT",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an RTM execution successfully committed",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Number of times RTM abort was triggered. (PEBS)",
        "EventCode": "0xC9",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "RTM_RETIRED.ABORTED",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
        "EventCode": "0xC9",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "RTM_RETIRED.ABORTED_MEM",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xC9",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "RTM_RETIRED.ABORTED_TIMER",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
        "EventCode": "0xC9",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
        "EventCode": "0xC9",
        "Counter": "0,1,2,3",
        "UMask": "0x40",
        "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
        "EventCode": "0xC9",
        "Counter": "0,1,2,3",
        "UMask": "0x80",
        "EventName": "RTM_RETIRED.ABORTED_EVENTS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PEBS": "2",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
        "EventCode": "0xCD",
        "MSRValue": "0x4",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
        "MSRIndex": "0x3F6",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.",
        "TakenAlone": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PEBS": "2",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
        "EventCode": "0xCD",
        "MSRValue": "0x8",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
        "MSRIndex": "0x3F6",
        "SampleAfterValue": "50021",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.",
        "TakenAlone": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PEBS": "2",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
        "EventCode": "0xCD",
        "MSRValue": "0x10",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
        "MSRIndex": "0x3F6",
        "SampleAfterValue": "20011",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.",
        "TakenAlone": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PEBS": "2",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
        "EventCode": "0xCD",
        "MSRValue": "0x20",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
        "MSRIndex": "0x3F6",
        "SampleAfterValue": "100007",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.",
        "TakenAlone": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PEBS": "2",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
        "EventCode": "0xCD",
        "MSRValue": "0x40",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
        "MSRIndex": "0x3F6",
        "SampleAfterValue": "2003",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.",
        "TakenAlone": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PEBS": "2",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
        "EventCode": "0xCD",
        "MSRValue": "0x80",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
        "MSRIndex": "0x3F6",
        "SampleAfterValue": "1009",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.",
        "TakenAlone": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PEBS": "2",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
        "EventCode": "0xCD",
        "MSRValue": "0x100",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
        "MSRIndex": "0x3F6",
        "SampleAfterValue": "503",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.",
        "TakenAlone": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PEBS": "2",
        "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
        "EventCode": "0xCD",
        "MSRValue": "0x200",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
        "MSRIndex": "0x3F6",
        "SampleAfterValue": "101",
        "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.",
        "TakenAlone": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3ffc000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS & ANY_SNOOP",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x103c000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_HITM",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x043c000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x023c000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_MISS",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x013c000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x00bc000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_NONE",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3fc4000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x1004000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0404000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0204000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0104000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0084000001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    }
]