summaryrefslogtreecommitdiffstats
path: root/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
blob: 254788af8ab6771f845752e6c52744b8b77a90ef (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
[
    {
        "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.  This event uses fixed counter 0.  You cannot collect a PEBs record for this event.",
        "EventCode": "0x00",
        "Counter": "Fixed counter 0",
        "UMask": "0x1",
        "EventName": "INST_RETIRED.ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Instructions retired (Fixed event)"
    },
    {
        "PublicDescription": "Counts the number of core cycles while the core is not in a halt state.  The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.  This event uses fixed counter 1.  You cannot collect a PEBs record for this event.",
        "EventCode": "0x00",
        "Counter": "Fixed counter 1",
        "UMask": "0x2",
        "EventName": "CPU_CLK_UNHALTED.CORE",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Core cycles when core is not halted  (Fixed event)"
    },
    {
        "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction.  In mobile systems the core frequency may change from time.  This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.  This event uses fixed counter 2.  You cannot collect a PEBs record for this event.",
        "EventCode": "0x00",
        "Counter": "Fixed counter 2",
        "UMask": "0x3",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Reference cycles when core is not halted  (Fixed event)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time.  The forward might occur subsequently when the data is available.",
        "EventCode": "0x03",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "LD_BLOCKS.DATA_UNKNOWN",
        "SampleAfterValue": "200003",
        "BriefDescription": "Loads blocked due to store data not ready (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.",
        "EventCode": "0x03",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "LD_BLOCKS.STORE_FORWARD",
        "SampleAfterValue": "200003",
        "BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.",
        "EventCode": "0x03",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "LD_BLOCKS.4K_ALIAS",
        "SampleAfterValue": "200003",
        "BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).",
        "EventCode": "0x03",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "LD_BLOCKS.UTLB_MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts anytime a load that retires is blocked for any reason.",
        "EventCode": "0x03",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "LD_BLOCKS.ALL_BLOCK",
        "SampleAfterValue": "200003",
        "BriefDescription": "Loads blocked (Precise event capable)"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine.  This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.",
        "EventCode": "0x0E",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EventName": "UOPS_ISSUED.ANY",
        "SampleAfterValue": "200003",
        "BriefDescription": "Uops issued to the back end per cycle"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Core cycles when core is not halted.  This event uses a (_P)rogrammable general purpose performance counter.",
        "EventCode": "0x3C",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EventName": "CPU_CLK_UNHALTED.CORE_P",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Core cycles when core is not halted"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Reference cycles when core is not halted.  This event uses a programmable general purpose performance counter.",
        "EventCode": "0x3C",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "CPU_CLK_UNHALTED.REF",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Reference cycles when core is not halted"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound.  When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources.  When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks.  However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all.  Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots.  These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots.  A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock.  The low uop issue rate for a stream of INC instructions is considered to be a back end issue.",
        "EventCode": "0x9C",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EventName": "UOPS_NOT_DELIVERED.ANY",
        "SampleAfterValue": "200003",
        "BriefDescription": "Uops requested but not-delivered to the back-end per cycle"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers.  This is an architectural performance event.  This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable:  The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.  Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.",
        "EventCode": "0xC0",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EventName": "INST_RETIRED.ANY_P",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Instructions retired (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts uops which retired.",
        "EventCode": "0xC2",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EventName": "UOPS_RETIRED.ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Uops retired (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts uops retired that are from the complex flows issued by the micro-sequencer (MS).  Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist.",
        "EventCode": "0xC2",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "UOPS_RETIRED.MS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "MS uops retired (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts the number of floating point divide uops retired.",
        "EventCode": "0xC2",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "UOPS_RETIRED.FPDIV",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Floating point divide uops retired. (Precise Event Capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts the number of integer divide uops retired.",
        "EventCode": "0xC2",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "UOPS_RETIRED.IDIV",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Integer divide uops retired. (Precise Event Capable)"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts machine clears for any reason.",
        "EventCode": "0xC3",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EventName": "MACHINE_CLEARS.ALL",
        "SampleAfterValue": "200003",
        "BriefDescription": "All machine clears"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification.  Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors.",
        "EventCode": "0xC3",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MACHINE_CLEARS.SMC",
        "SampleAfterValue": "200003",
        "BriefDescription": "Self-Modifying Code detected"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists.  For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.",
        "EventCode": "0xC3",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "MACHINE_CLEARS.FP_ASSIST",
        "SampleAfterValue": "200003",
        "BriefDescription": "Machine clears due to FP assists"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts machine clears due to memory disambiguation.  Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.",
        "EventCode": "0xC3",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "MACHINE_CLEARS.DISAMBIGUATION",
        "SampleAfterValue": "200003",
        "BriefDescription": "Machine clears due to memory disambiguation"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts branch instructions retired for all branch types.  This is an architectural performance event.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired branch instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0x7e",
        "EventName": "BR_INST_RETIRED.JCC",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired conditional branch instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts the number of taken branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0x80",
        "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired taken branch instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts far branch instructions retired.  This includes far jump, far call and return, and Interrupt call and return.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0xbf",
        "EventName": "BR_INST_RETIRED.FAR_BRANCH",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired far branch instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0xeb",
        "EventName": "BR_INST_RETIRED.NON_RETURN_IND",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts near return branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0xf7",
        "EventName": "BR_INST_RETIRED.RETURN",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired near return instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts near CALL branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0xf9",
        "EventName": "BR_INST_RETIRED.CALL",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired near call instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts near indirect CALL branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0xfb",
        "EventName": "BR_INST_RETIRED.IND_CALL",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired near indirect call instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts near relative CALL branch instructions retired.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0xfd",
        "EventName": "BR_INST_RETIRED.REL_CALL",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired near relative call instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken.",
        "EventCode": "0xC4",
        "Counter": "0,1,2,3",
        "UMask": "0xfe",
        "EventName": "BR_INST_RETIRED.TAKEN_JCC",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts mispredicted branch instructions retired including all branch types.",
        "EventCode": "0xC5",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired mispredicted branch instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition).",
        "EventCode": "0xC5",
        "Counter": "0,1,2,3",
        "UMask": "0x7e",
        "EventName": "BR_MISP_RETIRED.JCC",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted.",
        "EventCode": "0xC5",
        "Counter": "0,1,2,3",
        "UMask": "0xeb",
        "EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted.",
        "EventCode": "0xC5",
        "Counter": "0,1,2,3",
        "UMask": "0xf7",
        "EventName": "BR_MISP_RETIRED.RETURN",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired mispredicted near return instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted.",
        "EventCode": "0xC5",
        "Counter": "0,1,2,3",
        "UMask": "0xfb",
        "EventName": "BR_MISP_RETIRED.IND_CALL",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)"
    },
    {
        "PEBS": "2",
        "CollectPEBSRecord": "2",
        "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken.",
        "EventCode": "0xC5",
        "Counter": "0,1,2,3",
        "UMask": "0xfe",
        "EventName": "BR_MISP_RETIRED.TAKEN_JCC",
        "SampleAfterValue": "200003",
        "BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts core cycles if either divide unit is busy.",
        "EventCode": "0xCD",
        "Counter": "0,1,2,3",
        "UMask": "0x0",
        "EventName": "CYCLES_DIV_BUSY.ALL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles a divider is busy"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts core cycles the integer divide unit is busy.",
        "EventCode": "0xCD",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "CYCLES_DIV_BUSY.IDIV",
        "SampleAfterValue": "200003",
        "BriefDescription": "Cycles the integer divide unit is busy"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts core cycles the floating point divide unit is busy.",
        "EventCode": "0xCD",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "CYCLES_DIV_BUSY.FPDIV",
        "SampleAfterValue": "200003",
        "BriefDescription": "Cycles the FP divide unit is busy"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call,  Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.",
        "EventCode": "0xE6",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "BACLEARS.ALL",
        "SampleAfterValue": "200003",
        "BriefDescription": "BACLEARs asserted for any branch type"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts BACLEARS on return instructions.",
        "EventCode": "0xE6",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "BACLEARS.RETURN",
        "SampleAfterValue": "200003",
        "BriefDescription": "BACLEARs asserted for return branch"
    },
    {
        "CollectPEBSRecord": "1",
        "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.",
        "EventCode": "0xE6",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "BACLEARS.COND",
        "SampleAfterValue": "200003",
        "BriefDescription": "BACLEARs asserted for conditional branch"
    }
]