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/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2014 LSI Corporation
 */

#ifndef _DT_BINDINGS_CLK_AXM5516_H
#define _DT_BINDINGS_CLK_AXM5516_H

#define AXXIA_CLK_FAB_PLL	0
#define AXXIA_CLK_CPU_PLL	1
#define AXXIA_CLK_SYS_PLL	2
#define AXXIA_CLK_SM0_PLL	3
#define AXXIA_CLK_SM1_PLL	4
#define AXXIA_CLK_FAB_DIV	5
#define AXXIA_CLK_SYS_DIV	6
#define AXXIA_CLK_NRCP_DIV	7
#define AXXIA_CLK_CPU0_DIV	8
#define AXXIA_CLK_CPU1_DIV	9
#define AXXIA_CLK_CPU2_DIV	10
#define AXXIA_CLK_CPU3_DIV	11
#define AXXIA_CLK_PER_DIV	12
#define AXXIA_CLK_MMC_DIV	13
#define AXXIA_CLK_FAB		14
#define AXXIA_CLK_SYS		15
#define AXXIA_CLK_NRCP		16
#define AXXIA_CLK_CPU0		17
#define AXXIA_CLK_CPU1		18
#define AXXIA_CLK_CPU2		19
#define AXXIA_CLK_CPU3		20
#define AXXIA_CLK_PER		21
#define AXXIA_CLK_MMC		22

#endif