summaryrefslogtreecommitdiffstats
path: root/drivers/usb/phy/phy-tegra-usb.c
blob: f0240107edb15270d32ec67e19fe5dc200838665 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2010 Google, Inc.
 * Copyright (C) 2013 NVIDIA Corporation
 *
 * Author:
 *	Erik Gilling <konkers@google.com>
 *	Benoit Goby <benoit@android.com>
 *	Venu Byravarasu <vbyravarasu@nvidia.com>
 */

#include <linux/delay.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/gpio/consumer.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/resource.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include <linux/regulator/consumer.h>

#include <linux/usb/ehci_def.h>
#include <linux/usb/of.h>
#include <linux/usb/tegra_usb_phy.h>
#include <linux/usb/ulpi.h>

#define ULPI_VIEWPORT				0x170

/* PORTSC PTS/PHCD bits, Tegra20 only */
#define TEGRA_USB_PORTSC1			0x184
#define TEGRA_USB_PORTSC1_PTS(x)		(((x) & 0x3) << 30)
#define TEGRA_USB_PORTSC1_PHCD			BIT(23)

/* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
#define TEGRA_USB_HOSTPC1_DEVLC			0x1b4
#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x)		(((x) & 0x7) << 29)
#define TEGRA_USB_HOSTPC1_DEVLC_PHCD		BIT(22)

/* Bits of PORTSC1, which will get cleared by writing 1 into them */
#define TEGRA_PORTSC1_RWC_BITS	(PORT_CSC | PORT_PEC | PORT_OCC)

#define USB_SUSP_CTRL				0x400
#define   USB_WAKE_ON_RESUME_EN			BIT(2)
#define   USB_WAKE_ON_CNNT_EN_DEV		BIT(3)
#define   USB_WAKE_ON_DISCON_EN_DEV		BIT(4)
#define   USB_SUSP_CLR				BIT(5)
#define   USB_PHY_CLK_VALID			BIT(7)
#define   UTMIP_RESET				BIT(11)
#define   UHSIC_RESET				BIT(11)
#define   UTMIP_PHY_ENABLE			BIT(12)
#define   ULPI_PHY_ENABLE			BIT(13)
#define   USB_SUSP_SET				BIT(14)
#define   USB_WAKEUP_DEBOUNCE_COUNT(x)		(((x) & 0x7) << 16)

#define USB_PHY_VBUS_SENSORS			0x404
#define   B_SESS_VLD_WAKEUP_EN			BIT(14)
#define   A_SESS_VLD_WAKEUP_EN			BIT(22)
#define   A_VBUS_VLD_WAKEUP_EN			BIT(30)

#define USB_PHY_VBUS_WAKEUP_ID			0x408
#define   ID_INT_EN				BIT(0)
#define   ID_CHG_DET				BIT(1)
#define   VBUS_WAKEUP_INT_EN			BIT(8)
#define   VBUS_WAKEUP_CHG_DET			BIT(9)
#define   VBUS_WAKEUP_STS			BIT(10)
#define   VBUS_WAKEUP_WAKEUP_EN			BIT(30)

#define USB1_LEGACY_CTRL			0x410
#define   USB1_NO_LEGACY_MODE			BIT(0)
#define   USB1_VBUS_SENSE_CTL_MASK		(3 << 1)
#define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP	(0 << 1)
#define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
						(1 << 1)
#define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD	(2 << 1)
#define   USB1_VBUS_SENSE_CTL_A_SESS_VLD	(3 << 1)

#define ULPI_TIMING_CTRL_0			0x424
#define   ULPI_OUTPUT_PINMUX_BYP		BIT(10)
#define   ULPI_CLKOUT_PINMUX_BYP		BIT(11)

#define ULPI_TIMING_CTRL_1			0x428
#define   ULPI_DATA_TRIMMER_LOAD		BIT(0)
#define   ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
#define   ULPI_STPDIRNXT_TRIMMER_LOAD		BIT(16)
#define   ULPI_STPDIRNXT_TRIMMER_SEL(x)		(((x) & 0x7) << 17)
#define   ULPI_DIR_TRIMMER_LOAD			BIT(24)
#define   ULPI_DIR_TRIMMER_SEL(x)		(((x) & 0x7) << 25)

#define UTMIP_PLL_CFG1				0x804
#define   UTMIP_XTAL_FREQ_COUNT(x)		(((x) & 0xfff) << 0)
#define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)	(((x) & 0x1f) << 27)

#define UTMIP_XCVR_CFG0				0x808
#define   UTMIP_XCVR_SETUP(x)			(((x) & 0xf) << 0)
#define   UTMIP_XCVR_SETUP_MSB(x)		((((x) & 0x70) >> 4) << 22)
#define   UTMIP_XCVR_LSRSLEW(x)			(((x) & 0x3) << 8)
#define   UTMIP_XCVR_LSFSLEW(x)			(((x) & 0x3) << 10)
#define   UTMIP_FORCE_PD_POWERDOWN		BIT(14)
#define   UTMIP_FORCE_PD2_POWERDOWN		BIT(16)
#define   UTMIP_FORCE_PDZI_POWERDOWN		BIT(18)
#define   UTMIP_XCVR_LSBIAS_SEL			BIT(21)
#define   UTMIP_XCVR_HSSLEW(x)			(((x) & 0x3) << 4)
#define   UTMIP_XCVR_HSSLEW_MSB(x)		((((x) & 0x1fc) >> 2) << 25)

#define UTMIP_BIAS_CFG0				0x80c
#define   UTMIP_OTGPD				BIT(11)
#define   UTMIP_BIASPD				BIT(10)
#define   UTMIP_HSSQUELCH_LEVEL(x)		(((x) & 0x3) << 0)
#define   UTMIP_HSDISCON_LEVEL(x)		(((x) & 0x3) << 2)
#define   UTMIP_HSDISCON_LEVEL_MSB(x)		((((x) & 0x4) >> 2) << 24)

#define UTMIP_HSRX_CFG0				0x810
#define   UTMIP_ELASTIC_LIMIT(x)		(((x) & 0x1f) << 10)
#define   UTMIP_IDLE_WAIT(x)			(((x) & 0x1f) << 15)

#define UTMIP_HSRX_CFG1				0x814
#define   UTMIP_HS_SYNC_START_DLY(x)		(((x) & 0x1f) << 1)

#define UTMIP_TX_CFG0				0x820
#define   UTMIP_FS_PREABMLE_J			BIT(19)
#define   UTMIP_HS_DISCON_DISABLE		BIT(8)

#define UTMIP_MISC_CFG0				0x824
#define   UTMIP_DPDM_OBSERVE			BIT(26)
#define   UTMIP_DPDM_OBSERVE_SEL(x)		(((x) & 0xf) << 27)
#define   UTMIP_DPDM_OBSERVE_SEL_FS_J		UTMIP_DPDM_OBSERVE_SEL(0xf)
#define   UTMIP_DPDM_OBSERVE_SEL_FS_K		UTMIP_DPDM_OBSERVE_SEL(0xe)
#define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1		UTMIP_DPDM_OBSERVE_SEL(0xd)
#define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0		UTMIP_DPDM_OBSERVE_SEL(0xc)
#define   UTMIP_SUSPEND_EXIT_ON_EDGE		BIT(22)

#define UTMIP_MISC_CFG1				0x828
#define   UTMIP_PLL_ACTIVE_DLY_COUNT(x)		(((x) & 0x1f) << 18)
#define   UTMIP_PLLU_STABLE_COUNT(x)		(((x) & 0xfff) << 6)

#define UTMIP_DEBOUNCE_CFG0			0x82c
#define   UTMIP_BIAS_DEBOUNCE_A(x)		(((x) & 0xffff) << 0)

#define UTMIP_BAT_CHRG_CFG0			0x830
#define   UTMIP_PD_CHRG				BIT(0)

#define UTMIP_SPARE_CFG0			0x834
#define   FUSE_SETUP_SEL			BIT(3)

#define UTMIP_XCVR_CFG1				0x838
#define   UTMIP_FORCE_PDDISC_POWERDOWN		BIT(0)
#define   UTMIP_FORCE_PDCHRP_POWERDOWN		BIT(2)
#define   UTMIP_FORCE_PDDR_POWERDOWN		BIT(4)
#define   UTMIP_XCVR_TERM_RANGE_ADJ(x)		(((x) & 0xf) << 18)

#define UTMIP_BIAS_CFG1				0x83c
#define   UTMIP_BIAS_PDTRK_COUNT(x)		(((x) & 0x1f) << 3)

/* For Tegra30 and above only, the address is different in Tegra20 */
#define USB_USBMODE				0x1f8
#define   USB_USBMODE_MASK			(3 << 0)
#define   USB_USBMODE_HOST			(3 << 0)
#define   USB_USBMODE_DEVICE			(2 << 0)

#define PMC_USB_AO				0xf0
#define   VBUS_WAKEUP_PD_P0			BIT(2)
#define   ID_PD_P0				BIT(3)

static DEFINE_SPINLOCK(utmip_pad_lock);
static unsigned int utmip_pad_count;

struct tegra_xtal_freq {
	unsigned int freq;
	u8 enable_delay;
	u8 stable_count;
	u8 active_delay;
	u8 xtal_freq_count;
	u16 debounce;
};

static const struct tegra_xtal_freq tegra_freq_table[] = {
	{
		.freq = 12000000,
		.enable_delay = 0x02,
		.stable_count = 0x2F,
		.active_delay = 0x04,
		.xtal_freq_count = 0x76,
		.debounce = 0x7530,
	},
	{
		.freq = 13000000,
		.enable_delay = 0x02,
		.stable_count = 0x33,
		.active_delay = 0x05,
		.xtal_freq_count = 0x7F,
		.debounce = 0x7EF4,
	},
	{
		.freq = 19200000,
		.enable_delay = 0x03,
		.stable_count = 0x4B,
		.active_delay = 0x06,
		.xtal_freq_count = 0xBB,
		.debounce = 0xBB80,
	},
	{
		.freq = 26000000,
		.enable_delay = 0x04,
		.stable_count = 0x66,
		.active_delay = 0x09,
		.xtal_freq_count = 0xFE,
		.debounce = 0xFDE8,
	},
};

static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy)
{
	return container_of(u_phy, struct tegra_usb_phy, u_phy);
}

static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
{
	void __iomem *base = phy->regs;
	u32 val;

	if (phy->soc_config->has_hostpc) {
		val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
		val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
		val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
		writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
	} else {
		val = readl_relaxed(base + TEGRA_USB_PORTSC1);
		val &= ~TEGRA_PORTSC1_RWC_BITS;
		val &= ~TEGRA_USB_PORTSC1_PTS(~0);
		val |= TEGRA_USB_PORTSC1_PTS(pts_val);
		writel_relaxed(val, base + TEGRA_USB_PORTSC1);
	}
}

static void set_phcd(struct tegra_usb_phy *phy, bool enable)
{
	void __iomem *base = phy->regs;
	u32 val;

	if (phy->soc_config->has_hostpc) {
		val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
		if (enable)
			val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
		else
			val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
		writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
	} else {
		val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
		if (enable)
			val |= TEGRA_USB_PORTSC1_PHCD;
		else
			val &= ~TEGRA_USB_PORTSC1_PHCD;
		writel_relaxed(val, base + TEGRA_USB_PORTSC1);
	}
}

static int utmip_pad_open(struct tegra_usb_phy *phy)
{
	int ret;

	ret = clk_prepare_enable(phy->pad_clk);
	if (ret) {
		dev_err(phy->u_phy.dev,
			"Failed to enable UTMI-pads clock: %d\n", ret);
		return ret;
	}

	spin_lock(&utmip_pad_lock);

	ret = reset_control_deassert(phy->pad_rst);
	if (ret) {
		dev_err(phy->u_phy.dev,
			"Failed to initialize UTMI-pads reset: %d\n", ret);
		goto unlock;
	}

	ret = reset_control_assert(phy->pad_rst);
	if (ret) {
		dev_err(phy->u_phy.dev,
			"Failed to assert UTMI-pads reset: %d\n", ret);
		goto unlock;
	}

	udelay(1);

	ret = reset_control_deassert(phy->pad_rst);
	if (ret)
		dev_err(phy->u_phy.dev,
			"Failed to deassert UTMI-pads reset: %d\n", ret);
unlock:
	spin_unlock(&utmip_pad_lock);

	clk_disable_unprepare(phy->pad_clk);

	return ret;
}

static int utmip_pad_close(struct tegra_usb_phy *phy)
{
	int ret;

	ret = clk_prepare_enable(phy->pad_clk);
	if (ret) {
		dev_err(phy->u_phy.dev,
			"Failed to enable UTMI-pads clock: %d\n", ret);
		return ret;
	}

	ret = reset_control_assert(phy->pad_rst);
	if (ret)
		dev_err(phy->u_phy.dev,
			"Failed to assert UTMI-pads reset: %d\n", ret);

	udelay(1);

	clk_disable_unprepare(phy->pad_clk);

	return ret;
}

static int utmip_pad_power_on(struct tegra_usb_phy *phy)
{
	struct tegra_utmip_config *config = phy->config;
	void __iomem *base = phy->pad_regs;
	u32 val;
	int err;

	err = clk_prepare_enable(phy->pad_clk);
	if (err)
		return err;

	spin_lock(&utmip_pad_lock);

	if (utmip_pad_count++ == 0) {
		val = readl_relaxed(base + UTMIP_BIAS_CFG0);
		val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);

		if (phy->soc_config->requires_extra_tuning_parameters) {
			val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
				UTMIP_HSDISCON_LEVEL(~0) |
				UTMIP_HSDISCON_LEVEL_MSB(~0));

			val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
			val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
			val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
		}
		writel_relaxed(val, base + UTMIP_BIAS_CFG0);
	}

	if (phy->pad_wakeup) {
		phy->pad_wakeup = false;
		utmip_pad_count--;
	}

	spin_unlock(&utmip_pad_lock);

	clk_disable_unprepare(phy->pad_clk);

	return 0;
}

static int utmip_pad_power_off(struct tegra_usb_phy *phy)
{
	void __iomem *base = phy->pad_regs;
	u32 val;
	int ret;

	ret = clk_prepare_enable(phy->pad_clk);
	if (ret)
		return ret;

	spin_lock(&utmip_pad_lock);

	if (!utmip_pad_count) {
		dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
		ret = -EINVAL;
		goto ulock;
	}

	/*
	 * In accordance to TRM, OTG and Bias pad circuits could be turned off
	 * to save power if wake is enabled, but the VBUS-change detection
	 * method is board-specific and these circuits may need to be enabled
	 * to generate wakeup event, hence we will just keep them both enabled.
	 */
	if (phy->wakeup_enabled) {
		phy->pad_wakeup = true;
		utmip_pad_count++;
	}

	if (--utmip_pad_count == 0) {
		val = readl_relaxed(base + UTMIP_BIAS_CFG0);
		val |= UTMIP_OTGPD | UTMIP_BIASPD;
		writel_relaxed(val, base + UTMIP_BIAS_CFG0);
	}
ulock:
	spin_unlock(&utmip_pad_lock);

	clk_disable_unprepare(phy->pad_clk);

	return ret;
}

static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
{
	u32 tmp;

	return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result,
					  2000, 6000);
}

static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
{
	void __iomem *base = phy->regs;
	u32 val;

	/*
	 * The USB driver may have already initiated the phy clock
	 * disable so wait to see if the clock turns off and if not
	 * then proceed with gating the clock.
	 */
	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
		return;

	if (phy->is_legacy_phy) {
		val = readl_relaxed(base + USB_SUSP_CTRL);
		val |= USB_SUSP_SET;
		writel_relaxed(val, base + USB_SUSP_CTRL);

		usleep_range(10, 100);

		val = readl_relaxed(base + USB_SUSP_CTRL);
		val &= ~USB_SUSP_SET;
		writel_relaxed(val, base + USB_SUSP_CTRL);
	} else {
		set_phcd(phy, true);
	}

	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0))
		dev_err(phy->u_phy.dev,
			"Timeout waiting for PHY to stabilize on disable\n");
}

static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
{
	void __iomem *base = phy->regs;
	u32 val;

	/*
	 * The USB driver may have already initiated the phy clock
	 * enable so wait to see if the clock turns on and if not
	 * then proceed with ungating the clock.
	 */
	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
			       USB_PHY_CLK_VALID) == 0)
		return;

	if (phy->is_legacy_phy) {
		val = readl_relaxed(base + USB_SUSP_CTRL);
		val |= USB_SUSP_CLR;
		writel_relaxed(val, base + USB_SUSP_CTRL);

		usleep_range(10, 100);

		val = readl_relaxed(base + USB_SUSP_CTRL);
		val &= ~USB_SUSP_CLR;
		writel_relaxed(val, base + USB_SUSP_CTRL);
	} else {
		set_phcd(phy, false);
	}

	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
			       USB_PHY_CLK_VALID))
		dev_err(phy->u_phy.dev,
			"Timeout waiting for PHY to stabilize on enable\n");
}

static int utmi_phy_power_on(struct tegra_usb_phy *phy)
{
	struct tegra_utmip_config *config = phy->config;
	void __iomem *base = phy->regs;
	u32 val;
	int err;

	val = readl_relaxed(base + USB_SUSP_CTRL);
	val |= UTMIP_RESET;
	writel_relaxed(val, base + USB_SUSP_CTRL);

	if (phy->is_legacy_phy) {
		val = readl_relaxed(base + USB1_LEGACY_CTRL);
		val |= USB1_NO_LEGACY_MODE;
		writel_relaxed(val, base + USB1_LEGACY_CTRL);
	}

	val = readl_relaxed(base + UTMIP_TX_CFG0);
	val |= UTMIP_FS_PREABMLE_J;
	writel_relaxed(val, base + UTMIP_TX_CFG0);

	val = readl_relaxed(base + UTMIP_HSRX_CFG0);
	val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
	val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
	val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
	writel_relaxed(val, base + UTMIP_HSRX_CFG0);

	val = readl_relaxed(base + UTMIP_HSRX_CFG1);
	val &= ~UTMIP_HS_SYNC_START_DLY(~0);
	val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
	writel_relaxed(val, base + UTMIP_HSRX_CFG1);

	val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
	val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
	val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
	writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);

	val = readl_relaxed(base + UTMIP_MISC_CFG0);
	val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
	writel_relaxed(val, base + UTMIP_MISC_CFG0);

	if (!phy->soc_config->utmi_pll_config_in_car_module) {
		val = readl_relaxed(base + UTMIP_MISC_CFG1);
		val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
			UTMIP_PLLU_STABLE_COUNT(~0));
		val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
			UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
		writel_relaxed(val, base + UTMIP_MISC_CFG1);

		val = readl_relaxed(base + UTMIP_PLL_CFG1);
		val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
			UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
		val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
			UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
		writel_relaxed(val, base + UTMIP_PLL_CFG1);
	}

	val = readl_relaxed(base + USB_SUSP_CTRL);
	val &= ~USB_WAKE_ON_RESUME_EN;
	writel_relaxed(val, base + USB_SUSP_CTRL);

	if (phy->mode != USB_DR_MODE_HOST) {
		val = readl_relaxed(base + USB_SUSP_CTRL);
		val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
		writel_relaxed(val, base + USB_SUSP_CTRL);

		val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
		val &= ~VBUS_WAKEUP_WAKEUP_EN;
		val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET);
		writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);

		val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
		val &= ~(A_VBUS_VLD_WAKEUP_EN | A_SESS_VLD_WAKEUP_EN);
		val &= ~(B_SESS_VLD_WAKEUP_EN);
		writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);

		val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
		val &= ~UTMIP_PD_CHRG;
		writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
	} else {
		val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
		val |= UTMIP_PD_CHRG;
		writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
	}

	err = utmip_pad_power_on(phy);
	if (err)
		return err;

	val = readl_relaxed(base + UTMIP_XCVR_CFG0);
	val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
		 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
		 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
		 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));

	if (!config->xcvr_setup_use_fuses) {
		val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
		val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
	}
	val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
	val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);

	if (phy->soc_config->requires_extra_tuning_parameters) {
		val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
		val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
		val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
	}
	writel_relaxed(val, base + UTMIP_XCVR_CFG0);

	val = readl_relaxed(base + UTMIP_XCVR_CFG1);
	val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
		 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
	val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
	writel_relaxed(val, base + UTMIP_XCVR_CFG1);

	val = readl_relaxed(base + UTMIP_BIAS_CFG1);
	val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
	val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
	writel_relaxed(val, base + UTMIP_BIAS_CFG1);

	val = readl_relaxed(base + UTMIP_SPARE_CFG0);
	if (config->xcvr_setup_use_fuses)
		val |= FUSE_SETUP_SEL;
	else
		val &= ~FUSE_SETUP_SEL;
	writel_relaxed(val, base + UTMIP_SPARE_CFG0);

	if (!phy->is_legacy_phy) {
		val = readl_relaxed(base + USB_SUSP_CTRL);
		val |= UTMIP_PHY_ENABLE;
		writel_relaxed(val, base + USB_SUSP_CTRL);
	}

	val = readl_relaxed(base + USB_SUSP_CTRL);
	val &= ~UTMIP_RESET;
	writel_relaxed(val, base + USB_SUSP_CTRL);

	if (phy->is_legacy_phy) {
		val = readl_relaxed(base + USB1_LEGACY_CTRL);
		val &= ~USB1_VBUS_SENSE_CTL_MASK;
		val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
		writel_relaxed(val, base + USB1_LEGACY_CTRL);

		val = readl_relaxed(base + USB_SUSP_CTRL);
		val &= ~USB_SUSP_SET;
		writel_relaxed(val, base + USB_SUSP_CTRL);
	}

	utmi_phy_clk_enable(phy);

	if (phy->soc_config->requires_usbmode_setup) {
		val = readl_relaxed(base + USB_USBMODE);
		val &= ~USB_USBMODE_MASK;
		if (phy->mode == USB_DR_MODE_HOST)
			val |= USB_USBMODE_HOST;
		else
			val |= USB_USBMODE_DEVICE;
		writel_relaxed(val, base + USB_USBMODE);
	}

	if (!phy->is_legacy_phy)
		set_pts(phy, 0);

	return 0;
}

static int utmi_phy_power_off(struct tegra_usb_phy *phy)
{
	void __iomem *base = phy->regs;
	u32 val;

	/*
	 * Give hardware time to settle down after VBUS disconnection,
	 * otherwise PHY will immediately wake up from suspend.
	 */
	if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST)
		readl_relaxed_poll_timeout(base + USB_PHY_VBUS_WAKEUP_ID,
					   val, !(val & VBUS_WAKEUP_STS),
					   5000, 100000);

	utmi_phy_clk_disable(phy);

	/* PHY won't resume if reset is asserted */
	if (!phy->wakeup_enabled) {
		val = readl_relaxed(base + USB_SUSP_CTRL);
		val |= UTMIP_RESET;
		writel_relaxed(val, base + USB_SUSP_CTRL);
	}

	val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
	val |= UTMIP_PD_CHRG;
	writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);

	if (!phy->wakeup_enabled) {
		val = readl_relaxed(base + UTMIP_XCVR_CFG0);
		val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
		       UTMIP_FORCE_PDZI_POWERDOWN;
		writel_relaxed(val, base + UTMIP_XCVR_CFG0);
	}

	val = readl_relaxed(base + UTMIP_XCVR_CFG1);
	val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
	       UTMIP_FORCE_PDDR_POWERDOWN;
	writel_relaxed(val, base + UTMIP_XCVR_CFG1);

	if (phy->wakeup_enabled) {
		val = readl_relaxed(base + USB_SUSP_CTRL);
		val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
		val |= USB_WAKEUP_DEBOUNCE_COUNT(5);
		val |= USB_WAKE_ON_RESUME_EN;
		writel_relaxed(val, base + USB_SUSP_CTRL);

		/*
		 * Ask VBUS sensor to generate wake event once cable is
		 * connected.
		 */
		if (phy->mode != USB_DR_MODE_HOST) {
			val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
			val |= VBUS_WAKEUP_WAKEUP_EN;
			val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET);
			writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);

			val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
			val |= A_VBUS_VLD_WAKEUP_EN;
			writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);
		}
	}

	return utmip_pad_power_off(phy);
}

static void utmi_phy_preresume(struct tegra_usb_phy *phy)
{
	void __iomem *base = phy->regs;
	u32 val;

	val = readl_relaxed(base + UTMIP_TX_CFG0);
	val |= UTMIP_HS_DISCON_DISABLE;
	writel_relaxed(val, base + UTMIP_TX_CFG0);
}

static void utmi_phy_postresume(struct tegra_usb_phy *phy)
{
	void __iomem *base = phy->regs;
	u32 val;

	val = readl_relaxed(base + UTMIP_TX_CFG0);
	val &= ~UTMIP_HS_DISCON_DISABLE;
	writel_relaxed(val, base + UTMIP_TX_CFG0);
}

static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
				   enum tegra_usb_phy_port_speed port_speed)
{
	void __iomem *base = phy->regs;
	u32 val;

	val = readl_relaxed(base + UTMIP_MISC_CFG0);
	val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
	if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
		val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
	else
		val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
	writel_relaxed(val, base + UTMIP_MISC_CFG0);
	usleep_range(1, 10);

	val = readl_relaxed(base + UTMIP_MISC_CFG0);
	val |= UTMIP_DPDM_OBSERVE;
	writel_relaxed(val, base + UTMIP_MISC_CFG0);
	usleep_range(10, 100);
}

static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
{
	void __iomem *base = phy->regs;
	u32 val;

	val = readl_relaxed(base + UTMIP_MISC_CFG0);
	val &= ~UTMIP_DPDM_OBSERVE;
	writel_relaxed(val, base + UTMIP_MISC_CFG0);
	usleep_range(10, 100);
}

static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
{
	void __iomem *base = phy->regs;
	u32 val;
	int err;

	gpiod_set_value_cansleep(phy->reset_gpio, 1);

	err = clk_prepare_enable(phy->clk);
	if (err)
		return err;

	usleep_range(5000, 6000);

	gpiod_set_value_cansleep(phy->reset_gpio, 0);

	usleep_range(1000, 2000);

	val = readl_relaxed(base + USB_SUSP_CTRL);
	val |= UHSIC_RESET;
	writel_relaxed(val, base + USB_SUSP_CTRL);

	val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
	val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
	writel_relaxed(val, base + ULPI_TIMING_CTRL_0);

	val = readl_relaxed(base + USB_SUSP_CTRL);
	val |= ULPI_PHY_ENABLE;
	writel_relaxed(val, base + USB_SUSP_CTRL);

	val = 0;
	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);

	val |= ULPI_DATA_TRIMMER_SEL(4);
	val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
	val |= ULPI_DIR_TRIMMER_SEL(4);
	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
	usleep_range(10, 100);

	val |= ULPI_DATA_TRIMMER_LOAD;
	val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
	val |= ULPI_DIR_TRIMMER_LOAD;
	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);

	/* Fix VbusInvalid due to floating VBUS */
	err = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
	if (err) {
		dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
		goto disable_clk;
	}

	err = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
	if (err) {
		dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
		goto disable_clk;
	}

	val = readl_relaxed(base + USB_SUSP_CTRL);
	val |= USB_SUSP_CLR;
	writel_relaxed(val, base + USB_SUSP_CTRL);
	usleep_range(100, 1000);

	val = readl_relaxed(base + USB_SUSP_CTRL);
	val &= ~USB_SUSP_CLR;
	writel_relaxed(val, base + USB_SUSP_CTRL);

	return 0;

disable_clk:
	clk_disable_unprepare(phy->clk);

	return err;
}

static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
{
	gpiod_set_value_cansleep(phy->reset_gpio, 1);
	usleep_range(5000, 6000);
	clk_disable_unprepare(phy->clk);

	/*
	 * Wakeup currently unimplemented for ULPI, thus PHY needs to be
	 * force-resumed.
	 */
	if (WARN_ON_ONCE(phy->wakeup_enabled)) {
		ulpi_phy_power_on(phy);
		return -EOPNOTSUPP;
	}

	return 0;
}

static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
{
	int err;

	if (phy->powered_on)
		return 0;

	if (phy->is_ulpi_phy)
		err = ulpi_phy_power_on(phy);
	else
		err = utmi_phy_power_on(phy);
	if (err)
		return err;

	phy->powered_on = true;

	/* Let PHY settle down */
	usleep_range(2000, 2500);

	return 0;
}

static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
{
	int err;

	if (!phy->powered_on)
		return 0;

	if (phy->is_ulpi_phy)
		err = ulpi_phy_power_off(phy);
	else
		err = utmi_phy_power_off(phy);
	if (err)
		return err;

	phy->powered_on = false;

	return 0;
}

static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
{
	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);

	if (WARN_ON(!phy->freq))
		return;

	usb_phy_set_wakeup(u_phy, false);
	tegra_usb_phy_power_off(phy);

	if (!phy->is_ulpi_phy)
		utmip_pad_close(phy);

	regulator_disable(phy->vbus);
	clk_disable_unprepare(phy->pll_u);

	phy->freq = NULL;
}

static irqreturn_t tegra_usb_phy_isr(int irq, void *data)
{
	u32 val, int_mask = ID_CHG_DET | VBUS_WAKEUP_CHG_DET;
	struct tegra_usb_phy *phy = data;
	void __iomem *base = phy->regs;

	/*
	 * The PHY interrupt also wakes the USB controller driver since
	 * interrupt is shared. We don't do anything in the PHY driver,
	 * so just clear the interrupt.
	 */
	val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
	writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);

	return val & int_mask ? IRQ_HANDLED : IRQ_NONE;
}

static int tegra_usb_phy_set_wakeup(struct usb_phy *u_phy, bool enable)
{
	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
	void __iomem *base = phy->regs;
	int ret = 0;
	u32 val;

	if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST &&
	    phy->irq > 0) {
		disable_irq(phy->irq);

		val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
		val &= ~(ID_INT_EN | VBUS_WAKEUP_INT_EN);
		writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);

		enable_irq(phy->irq);

		free_irq(phy->irq, phy);

		phy->wakeup_enabled = false;
	}

	if (enable && phy->mode != USB_DR_MODE_HOST && phy->irq > 0) {
		ret = request_irq(phy->irq, tegra_usb_phy_isr, IRQF_SHARED,
				  dev_name(phy->u_phy.dev), phy);
		if (!ret) {
			disable_irq(phy->irq);

			/*
			 * USB clock will be resumed once wake event will be
			 * generated.  The ID-change event requires to have
			 * interrupts enabled, otherwise it won't be generated.
			 */
			val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
			val |= ID_INT_EN | VBUS_WAKEUP_INT_EN;
			writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);

			enable_irq(phy->irq);
		} else {
			dev_err(phy->u_phy.dev,
				"Failed to request interrupt: %d", ret);
			enable = false;
		}
	}

	phy->wakeup_enabled = enable;

	return ret;
}

static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
{
	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
	int ret;

	if (WARN_ON(!phy->freq))
		return -EINVAL;

	/*
	 * PHY is sharing IRQ with the CI driver, hence here we either
	 * disable interrupt for both PHY and CI or for CI only.  The
	 * interrupt needs to be disabled while hardware is reprogrammed
	 * because interrupt touches the programmed registers, and thus,
	 * there could be a race condition.
	 */
	if (phy->irq > 0)
		disable_irq(phy->irq);

	if (suspend)
		ret = tegra_usb_phy_power_off(phy);
	else
		ret = tegra_usb_phy_power_on(phy);

	if (phy->irq > 0)
		enable_irq(phy->irq);

	return ret;
}

static int tegra_usb_phy_configure_pmc(struct tegra_usb_phy *phy)
{
	int err, val = 0;

	/* older device-trees don't have PMC regmap */
	if (!phy->pmc_regmap)
		return 0;

	/*
	 * Tegra20 has a different layout of PMC USB register bits and AO is
	 * enabled by default after system reset on Tegra20, so assume nothing
	 * to do on Tegra20.
	 */
	if (!phy->soc_config->requires_pmc_ao_power_up)
		return 0;

	/* enable VBUS wake-up detector */
	if (phy->mode != USB_DR_MODE_HOST)
		val |= VBUS_WAKEUP_PD_P0 << phy->instance * 4;

	/* enable ID-pin ACC detector for OTG mode switching */
	if (phy->mode == USB_DR_MODE_OTG)
		val |= ID_PD_P0 << phy->instance * 4;

	/* disable detectors to reset them */
	err = regmap_set_bits(phy->pmc_regmap, PMC_USB_AO, val);
	if (err) {
		dev_err(phy->u_phy.dev, "Failed to disable PMC AO: %d\n", err);
		return err;
	}

	usleep_range(10, 100);

	/* enable detectors */
	err = regmap_clear_bits(phy->pmc_regmap, PMC_USB_AO, val);
	if (err) {
		dev_err(phy->u_phy.dev, "Failed to enable PMC AO: %d\n", err);
		return err;
	}

	/* detectors starts to work after 10ms */
	usleep_range(10000, 15000);

	return 0;
}

static int tegra_usb_phy_init(struct usb_phy *u_phy)
{
	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
	unsigned long parent_rate;
	unsigned int i;
	int err;

	if (WARN_ON(phy->freq))
		return 0;

	err = clk_prepare_enable(phy->pll_u);
	if (err)
		return err;

	parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
	for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
		if (tegra_freq_table[i].freq == parent_rate) {
			phy->freq = &tegra_freq_table[i];
			break;
		}
	}
	if (!phy->freq) {
		dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n",
			parent_rate);
		err = -EINVAL;
		goto disable_clk;
	}

	err = regulator_enable(phy->vbus);
	if (err) {
		dev_err(phy->u_phy.dev,
			"Failed to enable USB VBUS regulator: %d\n", err);
		goto disable_clk;
	}

	if (!phy->is_ulpi_phy) {
		err = utmip_pad_open(phy);
		if (err)
			goto disable_vbus;
	}

	err = tegra_usb_phy_configure_pmc(phy);
	if (err)
		goto close_phy;

	err = tegra_usb_phy_power_on(phy);
	if (err)
		goto close_phy;

	return 0;

close_phy:
	if (!phy->is_ulpi_phy)
		utmip_pad_close(phy);

disable_vbus:
	regulator_disable(phy->vbus);

disable_clk:
	clk_disable_unprepare(phy->pll_u);

	phy->freq = NULL;

	return err;
}

void tegra_usb_phy_preresume(struct usb_phy *u_phy)
{
	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);

	if (!phy->is_ulpi_phy)
		utmi_phy_preresume(phy);
}
EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);

void tegra_usb_phy_postresume(struct usb_phy *u_phy)
{
	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);

	if (!phy->is_ulpi_phy)
		utmi_phy_postresume(phy);
}
EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);

void tegra_ehci_phy_restore_start(struct usb_phy *u_phy,
				  enum tegra_usb_phy_port_speed port_speed)
{
	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);

	if (!phy->is_ulpi_phy)
		utmi_phy_restore_start(phy, port_speed);
}
EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);

void tegra_ehci_phy_restore_end(struct usb_phy *u_phy)
{
	struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);

	if (!phy->is_ulpi_phy)
		utmi_phy_restore_end(phy);
}
EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);

static int read_utmi_param(struct platform_device *pdev, const char *param,
			   u8 *dest)
{
	u32 value;
	int err;

	err = of_property_read_u32(pdev->dev.of_node, param, &value);
	if (err)
		dev_err(&pdev->dev,
			"Failed to read USB UTMI parameter %s: %d\n",
			param, err);
	else
		*dest = value;

	return err;
}

static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
			  struct platform_device *pdev)
{
	struct tegra_utmip_config *config;
	struct resource *res;
	int err;

	tegra_phy->is_ulpi_phy = false;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		dev_err(&pdev->dev, "Failed to get UTMI pad regs\n");
		return  -ENXIO;
	}

	/*
	 * Note that UTMI pad registers are shared by all PHYs, therefore
	 * devm_platform_ioremap_resource() can't be used here.
	 */
	tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
					   resource_size(res));
	if (!tegra_phy->pad_regs) {
		dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n");
		return -ENOMEM;
	}

	tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
					 GFP_KERNEL);
	if (!tegra_phy->config)
		return -ENOMEM;

	config = tegra_phy->config;

	err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
			      &config->hssync_start_delay);
	if (err)
		return err;

	err = read_utmi_param(pdev, "nvidia,elastic-limit",
			      &config->elastic_limit);
	if (err)
		return err;

	err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
			      &config->idle_wait_delay);
	if (err)
		return err;

	err = read_utmi_param(pdev, "nvidia,term-range-adj",
			      &config->term_range_adj);
	if (err)
		return err;

	err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
			      &config->xcvr_lsfslew);
	if (err)
		return err;

	err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
			      &config->xcvr_lsrslew);
	if (err)
		return err;

	if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
		err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
				      &config->xcvr_hsslew);
		if (err)
			return err;

		err = read_utmi_param(pdev, "nvidia,hssquelch-level",
				      &config->hssquelch_level);
		if (err)
			return err;

		err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
				      &config->hsdiscon_level);
		if (err)
			return err;
	}

	config->xcvr_setup_use_fuses = of_property_read_bool(
		pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");

	if (!config->xcvr_setup_use_fuses) {
		err = read_utmi_param(pdev, "nvidia,xcvr-setup",
				      &config->xcvr_setup);
		if (err)
			return err;
	}

	return 0;
}

static void tegra_usb_phy_put_pmc_device(void *dev)
{
	put_device(dev);
}

static int tegra_usb_phy_parse_pmc(struct device *dev,
				   struct tegra_usb_phy *phy)
{
	struct platform_device *pmc_pdev;
	struct of_phandle_args args;
	int err;

	err = of_parse_phandle_with_fixed_args(dev->of_node, "nvidia,pmc",
					       1, 0, &args);
	if (err) {
		if (err != -ENOENT)
			return err;

		dev_warn_once(dev, "nvidia,pmc is missing, please update your device-tree\n");
		return 0;
	}

	pmc_pdev = of_find_device_by_node(args.np);
	of_node_put(args.np);
	if (!pmc_pdev)
		return -ENODEV;

	err = devm_add_action_or_reset(dev, tegra_usb_phy_put_pmc_device,
				       &pmc_pdev->dev);
	if (err)
		return err;

	if (!platform_get_drvdata(pmc_pdev))
		return -EPROBE_DEFER;

	phy->pmc_regmap = dev_get_regmap(&pmc_pdev->dev, "usb_sleepwalk");
	if (!phy->pmc_regmap)
		return -EINVAL;

	phy->instance = args.args[0];

	return 0;
}

static const struct tegra_phy_soc_config tegra20_soc_config = {
	.utmi_pll_config_in_car_module = false,
	.has_hostpc = false,
	.requires_usbmode_setup = false,
	.requires_extra_tuning_parameters = false,
	.requires_pmc_ao_power_up = false,
};

static const struct tegra_phy_soc_config tegra30_soc_config = {
	.utmi_pll_config_in_car_module = true,
	.has_hostpc = true,
	.requires_usbmode_setup = true,
	.requires_extra_tuning_parameters = true,
	.requires_pmc_ao_power_up = true,
};

static const struct of_device_id tegra_usb_phy_id_table[] = {
	{ .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
	{ .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
	{ },
};
MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);

static int tegra_usb_phy_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct tegra_usb_phy *tegra_phy;
	enum usb_phy_interface phy_type;
	struct reset_control *reset;
	struct gpio_desc *gpiod;
	struct resource *res;
	struct usb_phy *phy;
	int err;

	tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
	if (!tegra_phy)
		return -ENOMEM;

	tegra_phy->soc_config = of_device_get_match_data(&pdev->dev);
	tegra_phy->irq = platform_get_irq_optional(pdev, 0);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "Failed to get I/O memory\n");
		return  -ENXIO;
	}

	/*
	 * Note that PHY and USB controller are using shared registers,
	 * therefore devm_platform_ioremap_resource() can't be used here.
	 */
	tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
				       resource_size(res));
	if (!tegra_phy->regs) {
		dev_err(&pdev->dev, "Failed to remap I/O memory\n");
		return -ENOMEM;
	}

	tegra_phy->is_legacy_phy =
		of_property_read_bool(np, "nvidia,has-legacy-mode");

	if (of_find_property(np, "dr_mode", NULL))
		tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
	else
		tegra_phy->mode = USB_DR_MODE_HOST;

	if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
		dev_err(&pdev->dev, "dr_mode is invalid\n");
		return -EINVAL;
	}

	/* On some boards, the VBUS regulator doesn't need to be controlled */
	tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
	if (IS_ERR(tegra_phy->vbus))
		return PTR_ERR(tegra_phy->vbus);

	tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u");
	err = PTR_ERR_OR_ZERO(tegra_phy->pll_u);
	if (err) {
		dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err);
		return err;
	}

	err = tegra_usb_phy_parse_pmc(&pdev->dev, tegra_phy);
	if (err) {
		dev_err_probe(&pdev->dev, err, "Failed to get PMC regmap\n");
		return err;
	}

	phy_type = of_usb_get_phy_mode(np);
	switch (phy_type) {
	case USBPHY_INTERFACE_MODE_UTMI:
		err = utmi_phy_probe(tegra_phy, pdev);
		if (err)
			return err;

		tegra_phy->pad_clk = devm_clk_get(&pdev->dev, "utmi-pads");
		err = PTR_ERR_OR_ZERO(tegra_phy->pad_clk);
		if (err) {
			dev_err(&pdev->dev,
				"Failed to get UTMIP pad clock: %d\n", err);
			return err;
		}

		reset = devm_reset_control_get_optional_shared(&pdev->dev,
							       "utmi-pads");
		err = PTR_ERR_OR_ZERO(reset);
		if (err) {
			dev_err(&pdev->dev,
				"Failed to get UTMI-pads reset: %d\n", err);
			return err;
		}
		tegra_phy->pad_rst = reset;
		break;

	case USBPHY_INTERFACE_MODE_ULPI:
		tegra_phy->is_ulpi_phy = true;

		tegra_phy->clk = devm_clk_get(&pdev->dev, "ulpi-link");
		err = PTR_ERR_OR_ZERO(tegra_phy->clk);
		if (err) {
			dev_err(&pdev->dev,
				"Failed to get ULPI clock: %d\n", err);
			return err;
		}

		gpiod = devm_gpiod_get(&pdev->dev, "nvidia,phy-reset",
				       GPIOD_OUT_HIGH);
		err = PTR_ERR_OR_ZERO(gpiod);
		if (err) {
			dev_err(&pdev->dev,
				"Request failed for reset GPIO: %d\n", err);
			return err;
		}

		err = gpiod_set_consumer_name(gpiod, "ulpi_phy_reset_b");
		if (err) {
			dev_err(&pdev->dev,
				"Failed to set up reset GPIO name: %d\n", err);
			return err;
		}

		tegra_phy->reset_gpio = gpiod;

		phy = devm_otg_ulpi_create(&pdev->dev,
					   &ulpi_viewport_access_ops, 0);
		if (!phy) {
			dev_err(&pdev->dev, "Failed to create ULPI OTG\n");
			return -ENOMEM;
		}

		tegra_phy->ulpi = phy;
		tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT;
		break;

	default:
		dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
			phy_type);
		return -EINVAL;
	}

	tegra_phy->u_phy.dev = &pdev->dev;
	tegra_phy->u_phy.init = tegra_usb_phy_init;
	tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown;
	tegra_phy->u_phy.set_wakeup = tegra_usb_phy_set_wakeup;
	tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend;

	platform_set_drvdata(pdev, tegra_phy);

	return usb_add_phy_dev(&tegra_phy->u_phy);
}

static int tegra_usb_phy_remove(struct platform_device *pdev)
{
	struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);

	usb_remove_phy(&tegra_phy->u_phy);

	return 0;
}

static struct platform_driver tegra_usb_phy_driver = {
	.probe		= tegra_usb_phy_probe,
	.remove		= tegra_usb_phy_remove,
	.driver		= {
		.name	= "tegra-phy",
		.of_match_table = tegra_usb_phy_id_table,
	},
};
module_platform_driver(tegra_usb_phy_driver);

MODULE_DESCRIPTION("Tegra USB PHY driver");
MODULE_LICENSE("GPL v2");