summaryrefslogtreecommitdiffstats
path: root/drivers/mtd/nand/raw/ingenic/jz4725b_bch.c
blob: 2d0e0a2192ae4dcb9956341a9eeed782ad08a15a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
// SPDX-License-Identifier: GPL-2.0
/*
 * JZ4725B BCH controller driver
 *
 * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
 *
 * Based on jz4780_bch.c
 */

#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>

#include "ingenic_ecc.h"

#define BCH_BHCR			0x0
#define BCH_BHCSR			0x4
#define BCH_BHCCR			0x8
#define BCH_BHCNT			0xc
#define BCH_BHDR			0x10
#define BCH_BHPAR0			0x14
#define BCH_BHERR0			0x28
#define BCH_BHINT			0x24
#define BCH_BHINTES			0x3c
#define BCH_BHINTEC			0x40
#define BCH_BHINTE			0x38

#define BCH_BHCR_ENCE			BIT(3)
#define BCH_BHCR_BSEL			BIT(2)
#define BCH_BHCR_INIT			BIT(1)
#define BCH_BHCR_BCHE			BIT(0)

#define BCH_BHCNT_DEC_COUNT_SHIFT	16
#define BCH_BHCNT_DEC_COUNT_MASK	(0x3ff << BCH_BHCNT_DEC_COUNT_SHIFT)
#define BCH_BHCNT_ENC_COUNT_SHIFT	0
#define BCH_BHCNT_ENC_COUNT_MASK	(0x3ff << BCH_BHCNT_ENC_COUNT_SHIFT)

#define BCH_BHERR_INDEX0_SHIFT		0
#define BCH_BHERR_INDEX0_MASK		(0x1fff << BCH_BHERR_INDEX0_SHIFT)
#define BCH_BHERR_INDEX1_SHIFT		16
#define BCH_BHERR_INDEX1_MASK		(0x1fff << BCH_BHERR_INDEX1_SHIFT)

#define BCH_BHINT_ERRC_SHIFT		28
#define BCH_BHINT_ERRC_MASK		(0xf << BCH_BHINT_ERRC_SHIFT)
#define BCH_BHINT_TERRC_SHIFT		16
#define BCH_BHINT_TERRC_MASK		(0x7f << BCH_BHINT_TERRC_SHIFT)
#define BCH_BHINT_ALL_0			BIT(5)
#define BCH_BHINT_ALL_F			BIT(4)
#define BCH_BHINT_DECF			BIT(3)
#define BCH_BHINT_ENCF			BIT(2)
#define BCH_BHINT_UNCOR			BIT(1)
#define BCH_BHINT_ERR			BIT(0)

/* Timeout for BCH calculation/correction. */
#define BCH_TIMEOUT_US			100000

static inline void jz4725b_bch_config_set(struct ingenic_ecc *bch, u32 cfg)
{
	writel(cfg, bch->base + BCH_BHCSR);
}

static inline void jz4725b_bch_config_clear(struct ingenic_ecc *bch, u32 cfg)
{
	writel(cfg, bch->base + BCH_BHCCR);
}

static int jz4725b_bch_reset(struct ingenic_ecc *bch,
			     struct ingenic_ecc_params *params, bool calc_ecc)
{
	u32 reg, max_value;

	/* Clear interrupt status. */
	writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);

	/* Initialise and enable BCH. */
	jz4725b_bch_config_clear(bch, 0x1f);
	jz4725b_bch_config_set(bch, BCH_BHCR_BCHE);

	if (params->strength == 8)
		jz4725b_bch_config_set(bch, BCH_BHCR_BSEL);
	else
		jz4725b_bch_config_clear(bch, BCH_BHCR_BSEL);

	if (calc_ecc) /* calculate ECC from data */
		jz4725b_bch_config_set(bch, BCH_BHCR_ENCE);
	else /* correct data from ECC */
		jz4725b_bch_config_clear(bch, BCH_BHCR_ENCE);

	jz4725b_bch_config_set(bch, BCH_BHCR_INIT);

	max_value = BCH_BHCNT_ENC_COUNT_MASK >> BCH_BHCNT_ENC_COUNT_SHIFT;
	if (params->size > max_value)
		return -EINVAL;

	max_value = BCH_BHCNT_DEC_COUNT_MASK >> BCH_BHCNT_DEC_COUNT_SHIFT;
	if (params->size + params->bytes > max_value)
		return -EINVAL;

	/* Set up BCH count register. */
	reg = params->size << BCH_BHCNT_ENC_COUNT_SHIFT;
	reg |= (params->size + params->bytes) << BCH_BHCNT_DEC_COUNT_SHIFT;
	writel(reg, bch->base + BCH_BHCNT);

	return 0;
}

static void jz4725b_bch_disable(struct ingenic_ecc *bch)
{
	/* Clear interrupts */
	writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);

	/* Disable the hardware */
	jz4725b_bch_config_clear(bch, BCH_BHCR_BCHE);
}

static void jz4725b_bch_write_data(struct ingenic_ecc *bch, const u8 *buf,
				   size_t size)
{
	while (size--)
		writeb(*buf++, bch->base + BCH_BHDR);
}

static void jz4725b_bch_read_parity(struct ingenic_ecc *bch, u8 *buf,
				    size_t size)
{
	size_t size32 = size / sizeof(u32);
	size_t size8 = size % sizeof(u32);
	u32 *dest32;
	u8 *dest8;
	u32 val, offset = 0;

	dest32 = (u32 *)buf;
	while (size32--) {
		*dest32++ = readl_relaxed(bch->base + BCH_BHPAR0 + offset);
		offset += sizeof(u32);
	}

	dest8 = (u8 *)dest32;
	val = readl_relaxed(bch->base + BCH_BHPAR0 + offset);
	switch (size8) {
	case 3:
		dest8[2] = (val >> 16) & 0xff;
		fallthrough;
	case 2:
		dest8[1] = (val >> 8) & 0xff;
		fallthrough;
	case 1:
		dest8[0] = val & 0xff;
		break;
	}
}

static int jz4725b_bch_wait_complete(struct ingenic_ecc *bch, unsigned int irq,
				     u32 *status)
{
	u32 reg;
	int ret;

	/*
	 * While we could use interrupts here and sleep until the operation
	 * completes, the controller works fairly quickly (usually a few
	 * microseconds) and so the overhead of sleeping until we get an
	 * interrupt quite noticeably decreases performance.
	 */
	ret = readl_relaxed_poll_timeout(bch->base + BCH_BHINT, reg,
					 reg & irq, 0, BCH_TIMEOUT_US);
	if (ret)
		return ret;

	if (status)
		*status = reg;

	writel(reg, bch->base + BCH_BHINT);

	return 0;
}

static int jz4725b_calculate(struct ingenic_ecc *bch,
			     struct ingenic_ecc_params *params,
			     const u8 *buf, u8 *ecc_code)
{
	int ret;

	mutex_lock(&bch->lock);

	ret = jz4725b_bch_reset(bch, params, true);
	if (ret) {
		dev_err(bch->dev, "Unable to init BCH with given parameters\n");
		goto out_disable;
	}

	jz4725b_bch_write_data(bch, buf, params->size);

	ret = jz4725b_bch_wait_complete(bch, BCH_BHINT_ENCF, NULL);
	if (ret) {
		dev_err(bch->dev, "timed out while calculating ECC\n");
		goto out_disable;
	}

	jz4725b_bch_read_parity(bch, ecc_code, params->bytes);

out_disable:
	jz4725b_bch_disable(bch);
	mutex_unlock(&bch->lock);

	return ret;
}

static int jz4725b_correct(struct ingenic_ecc *bch,
			   struct ingenic_ecc_params *params,
			   u8 *buf, u8 *ecc_code)
{
	u32 reg, errors, bit;
	unsigned int i;
	int ret;

	mutex_lock(&bch->lock);

	ret = jz4725b_bch_reset(bch, params, false);
	if (ret) {
		dev_err(bch->dev, "Unable to init BCH with given parameters\n");
		goto out;
	}

	jz4725b_bch_write_data(bch, buf, params->size);
	jz4725b_bch_write_data(bch, ecc_code, params->bytes);

	ret = jz4725b_bch_wait_complete(bch, BCH_BHINT_DECF, &reg);
	if (ret) {
		dev_err(bch->dev, "timed out while correcting data\n");
		goto out;
	}

	if (reg & (BCH_BHINT_ALL_F | BCH_BHINT_ALL_0)) {
		/* Data and ECC is all 0xff or 0x00 - nothing to correct */
		ret = 0;
		goto out;
	}

	if (reg & BCH_BHINT_UNCOR) {
		/* Uncorrectable ECC error */
		ret = -EBADMSG;
		goto out;
	}

	errors = (reg & BCH_BHINT_ERRC_MASK) >> BCH_BHINT_ERRC_SHIFT;

	/* Correct any detected errors. */
	for (i = 0; i < errors; i++) {
		if (i & 1) {
			bit = (reg & BCH_BHERR_INDEX1_MASK) >> BCH_BHERR_INDEX1_SHIFT;
		} else {
			reg = readl(bch->base + BCH_BHERR0 + (i * 4));
			bit = (reg & BCH_BHERR_INDEX0_MASK) >> BCH_BHERR_INDEX0_SHIFT;
		}

		buf[(bit >> 3)] ^= BIT(bit & 0x7);
	}

out:
	jz4725b_bch_disable(bch);
	mutex_unlock(&bch->lock);

	return ret;
}

static const struct ingenic_ecc_ops jz4725b_bch_ops = {
	.disable = jz4725b_bch_disable,
	.calculate = jz4725b_calculate,
	.correct = jz4725b_correct,
};

static const struct of_device_id jz4725b_bch_dt_match[] = {
	{ .compatible = "ingenic,jz4725b-bch", .data = &jz4725b_bch_ops },
	{},
};
MODULE_DEVICE_TABLE(of, jz4725b_bch_dt_match);

static struct platform_driver jz4725b_bch_driver = {
	.probe		= ingenic_ecc_probe,
	.driver	= {
		.name	= "jz4725b-bch",
		.of_match_table = jz4725b_bch_dt_match,
	},
};
module_platform_driver(jz4725b_bch_driver);

MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
MODULE_DESCRIPTION("Ingenic JZ4725B BCH controller driver");
MODULE_LICENSE("GPL v2");