summaryrefslogtreecommitdiffstats
path: root/drivers/mfd/ioc3.c
blob: c73ec78f255ba694d2bfe923c37960c2f52b9984 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
// SPDX-License-Identifier: GPL-2.0
/*
 * SGI IOC3 multifunction device driver
 *
 * Copyright (C) 2018, 2019 Thomas Bogendoerfer <tbogendoerfer@suse.de>
 *
 * Based on work by:
 *   Stanislaw Skowronek <skylark@unaligned.org>
 *   Joshua Kinard <kumba@gentoo.org>
 *   Brent Casavant <bcasavan@sgi.com> - IOC4 master driver
 *   Pat Gefre <pfg@sgi.com> - IOC3 serial port IRQ demuxer
 */

#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/platform_data/sgi-w1.h>
#include <linux/rtc/ds1685.h>

#include <asm/pci/bridge.h>
#include <asm/sn/ioc3.h>

#define IOC3_IRQ_SERIAL_A	6
#define IOC3_IRQ_SERIAL_B	15
#define IOC3_IRQ_KBD		22

/* Bitmask for selecting which IRQs are level triggered */
#define IOC3_LVL_MASK	(BIT(IOC3_IRQ_SERIAL_A) | BIT(IOC3_IRQ_SERIAL_B))

#define M48T35_REG_SIZE	32768	/* size of m48t35 registers */

/* 1.2 us latency timer (40 cycles at 33 MHz) */
#define IOC3_LATENCY	40

struct ioc3_priv_data {
	struct irq_domain *domain;
	struct ioc3 __iomem *regs;
	struct pci_dev *pdev;
	int domain_irq;
};

static void ioc3_irq_ack(struct irq_data *d)
{
	struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
	unsigned int hwirq = irqd_to_hwirq(d);

	writel(BIT(hwirq), &ipd->regs->sio_ir);
}

static void ioc3_irq_mask(struct irq_data *d)
{
	struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
	unsigned int hwirq = irqd_to_hwirq(d);

	writel(BIT(hwirq), &ipd->regs->sio_iec);
}

static void ioc3_irq_unmask(struct irq_data *d)
{
	struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
	unsigned int hwirq = irqd_to_hwirq(d);

	writel(BIT(hwirq), &ipd->regs->sio_ies);
}

static struct irq_chip ioc3_irq_chip = {
	.name		= "IOC3",
	.irq_ack	= ioc3_irq_ack,
	.irq_mask	= ioc3_irq_mask,
	.irq_unmask	= ioc3_irq_unmask,
};

static int ioc3_irq_domain_map(struct irq_domain *d, unsigned int irq,
			      irq_hw_number_t hwirq)
{
	/* Set level IRQs for every interrupt contained in IOC3_LVL_MASK */
	if (BIT(hwirq) & IOC3_LVL_MASK)
		irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_level_irq);
	else
		irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_edge_irq);

	irq_set_chip_data(irq, d->host_data);
	return 0;
}

static void ioc3_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
{
	irq_set_chip_and_handler(irq, NULL, NULL);
	irq_set_chip_data(irq, NULL);
}

static const struct irq_domain_ops ioc3_irq_domain_ops = {
	.map = ioc3_irq_domain_map,
	.unmap = ioc3_irq_domain_unmap,
};

static void ioc3_irq_handler(struct irq_desc *desc)
{
	struct irq_domain *domain = irq_desc_get_handler_data(desc);
	struct ioc3_priv_data *ipd = domain->host_data;
	struct ioc3 __iomem *regs = ipd->regs;
	u32 pending, mask;
	unsigned int irq;

	pending = readl(&regs->sio_ir);
	mask = readl(&regs->sio_ies);
	pending &= mask; /* Mask off not enabled interrupts */

	if (pending) {
		irq = irq_find_mapping(domain, __ffs(pending));
		if (irq)
			generic_handle_irq(irq);
	} else  {
		spurious_interrupt();
	}
}

/*
 * System boards/BaseIOs use more interrupt pins of the bridge ASIC
 * to which the IOC3 is connected. Since the IOC3 MFD driver
 * knows wiring of these extra pins, we use the map_irq function
 * to get interrupts activated
 */
static int ioc3_map_irq(struct pci_dev *pdev, int slot, int pin)
{
	struct pci_host_bridge *hbrg = pci_find_host_bridge(pdev->bus);

	return hbrg->map_irq(pdev, slot, pin);
}

static int ioc3_irq_domain_setup(struct ioc3_priv_data *ipd, int irq)
{
	struct irq_domain *domain;
	struct fwnode_handle *fn;

	fn = irq_domain_alloc_named_fwnode("IOC3");
	if (!fn)
		goto err;

	domain = irq_domain_create_linear(fn, 24, &ioc3_irq_domain_ops, ipd);
	if (!domain) {
		irq_domain_free_fwnode(fn);
		goto err;
	}

	ipd->domain = domain;

	irq_set_chained_handler_and_data(irq, ioc3_irq_handler, domain);
	ipd->domain_irq = irq;
	return 0;

err:
	dev_err(&ipd->pdev->dev, "irq domain setup failed\n");
	return -ENOMEM;
}

static const struct resource ioc3_uarta_resources[] = {
	DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uarta),
		       sizeof_field(struct ioc3, sregs.uarta)),
	DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_A)
};

static const struct resource ioc3_uartb_resources[] = {
	DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uartb),
		       sizeof_field(struct ioc3, sregs.uartb)),
	DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_B)
};

static struct mfd_cell ioc3_serial_cells[] = {
	{
		.name = "ioc3-serial8250",
		.resources = ioc3_uarta_resources,
		.num_resources = ARRAY_SIZE(ioc3_uarta_resources),
	},
	{
		.name = "ioc3-serial8250",
		.resources = ioc3_uartb_resources,
		.num_resources = ARRAY_SIZE(ioc3_uartb_resources),
	}
};

static int ioc3_serial_setup(struct ioc3_priv_data *ipd)
{
	int ret;

	/* Set gpio pins for RS232/RS422 mode selection */
	writel(GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL,
		&ipd->regs->gpcr_s);
	/* Select RS232 mode for uart a */
	writel(0, &ipd->regs->gppr[6]);
	/* Select RS232 mode for uart b */
	writel(0, &ipd->regs->gppr[7]);

	/* Switch both ports to 16650 mode */
	writel(readl(&ipd->regs->port_a.sscr) & ~SSCR_DMA_EN,
	       &ipd->regs->port_a.sscr);
	writel(readl(&ipd->regs->port_b.sscr) & ~SSCR_DMA_EN,
	       &ipd->regs->port_b.sscr);
	udelay(1000); /* Wait until mode switch is done */

	ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
			      ioc3_serial_cells, ARRAY_SIZE(ioc3_serial_cells),
			      &ipd->pdev->resource[0], 0, ipd->domain);
	if (ret) {
		dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
		return ret;
	}

	return 0;
}

static const struct resource ioc3_kbd_resources[] = {
	DEFINE_RES_MEM(offsetof(struct ioc3, serio),
		       sizeof_field(struct ioc3, serio)),
	DEFINE_RES_IRQ(IOC3_IRQ_KBD)
};

static struct mfd_cell ioc3_kbd_cells[] = {
	{
		.name = "ioc3-kbd",
		.resources = ioc3_kbd_resources,
		.num_resources = ARRAY_SIZE(ioc3_kbd_resources),
	}
};

static int ioc3_kbd_setup(struct ioc3_priv_data *ipd)
{
	int ret;

	ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
			      ioc3_kbd_cells, ARRAY_SIZE(ioc3_kbd_cells),
			      &ipd->pdev->resource[0], 0, ipd->domain);
	if (ret) {
		dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
		return ret;
	}

	return 0;
}

static const struct resource ioc3_eth_resources[] = {
	DEFINE_RES_MEM(offsetof(struct ioc3, eth),
		       sizeof_field(struct ioc3, eth)),
	DEFINE_RES_MEM(offsetof(struct ioc3, ssram),
		       sizeof_field(struct ioc3, ssram)),
	DEFINE_RES_IRQ(0)
};

static const struct resource ioc3_w1_resources[] = {
	DEFINE_RES_MEM(offsetof(struct ioc3, mcr),
		       sizeof_field(struct ioc3, mcr)),
};
static struct sgi_w1_platform_data ioc3_w1_platform_data;

static struct mfd_cell ioc3_eth_cells[] = {
	{
		.name = "ioc3-eth",
		.resources = ioc3_eth_resources,
		.num_resources = ARRAY_SIZE(ioc3_eth_resources),
	},
	{
		.name = "sgi_w1",
		.resources = ioc3_w1_resources,
		.num_resources = ARRAY_SIZE(ioc3_w1_resources),
		.platform_data = &ioc3_w1_platform_data,
		.pdata_size = sizeof(ioc3_w1_platform_data),
	}
};

static int ioc3_eth_setup(struct ioc3_priv_data *ipd)
{
	int ret;

	/* Enable One-Wire bus */
	writel(GPCR_MLAN_EN, &ipd->regs->gpcr_s);

	/* Generate unique identifier */
	snprintf(ioc3_w1_platform_data.dev_id,
		 sizeof(ioc3_w1_platform_data.dev_id), "ioc3-%012llx",
		 ipd->pdev->resource->start);

	ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
			      ioc3_eth_cells, ARRAY_SIZE(ioc3_eth_cells),
			      &ipd->pdev->resource[0], ipd->pdev->irq, NULL);
	if (ret) {
		dev_err(&ipd->pdev->dev, "Failed to add ETH/W1 subdev\n");
		return ret;
	}

	return 0;
}

static const struct resource ioc3_m48t35_resources[] = {
	DEFINE_RES_MEM(IOC3_BYTEBUS_DEV0, M48T35_REG_SIZE)
};

static struct mfd_cell ioc3_m48t35_cells[] = {
	{
		.name = "rtc-m48t35",
		.resources = ioc3_m48t35_resources,
		.num_resources = ARRAY_SIZE(ioc3_m48t35_resources),
	}
};

static int ioc3_m48t35_setup(struct ioc3_priv_data *ipd)
{
	int ret;

	ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
			      ioc3_m48t35_cells, ARRAY_SIZE(ioc3_m48t35_cells),
			      &ipd->pdev->resource[0], 0, ipd->domain);
	if (ret)
		dev_err(&ipd->pdev->dev, "Failed to add M48T35 subdev\n");

	return ret;
}

static struct ds1685_rtc_platform_data ip30_rtc_platform_data = {
	.bcd_mode = false,
	.no_irq = false,
	.uie_unsupported = true,
	.access_type = ds1685_reg_indirect,
};

static const struct resource ioc3_rtc_ds1685_resources[] = {
	DEFINE_RES_MEM(IOC3_BYTEBUS_DEV1, 1),
	DEFINE_RES_MEM(IOC3_BYTEBUS_DEV2, 1),
	DEFINE_RES_IRQ(0)
};

static struct mfd_cell ioc3_ds1685_cells[] = {
	{
		.name = "rtc-ds1685",
		.resources = ioc3_rtc_ds1685_resources,
		.num_resources = ARRAY_SIZE(ioc3_rtc_ds1685_resources),
		.platform_data = &ip30_rtc_platform_data,
		.pdata_size = sizeof(ip30_rtc_platform_data),
		.id = PLATFORM_DEVID_NONE,
	}
};

static int ioc3_ds1685_setup(struct ioc3_priv_data *ipd)
{
	int ret, irq;

	irq = ioc3_map_irq(ipd->pdev, 6, 0);

	ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_ds1685_cells,
			      ARRAY_SIZE(ioc3_ds1685_cells),
			      &ipd->pdev->resource[0], irq, NULL);
	if (ret)
		dev_err(&ipd->pdev->dev, "Failed to add DS1685 subdev\n");

	return ret;
};


static const struct resource ioc3_leds_resources[] = {
	DEFINE_RES_MEM(offsetof(struct ioc3, gppr[0]),
		       sizeof_field(struct ioc3, gppr[0])),
	DEFINE_RES_MEM(offsetof(struct ioc3, gppr[1]),
		       sizeof_field(struct ioc3, gppr[1])),
};

static struct mfd_cell ioc3_led_cells[] = {
	{
		.name = "ip30-leds",
		.resources = ioc3_leds_resources,
		.num_resources = ARRAY_SIZE(ioc3_leds_resources),
		.id = PLATFORM_DEVID_NONE,
	}
};

static int ioc3_led_setup(struct ioc3_priv_data *ipd)
{
	int ret;

	ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_led_cells,
			      ARRAY_SIZE(ioc3_led_cells),
			      &ipd->pdev->resource[0], 0, ipd->domain);
	if (ret)
		dev_err(&ipd->pdev->dev, "Failed to add LED subdev\n");

	return ret;
}

static int ip27_baseio_setup(struct ioc3_priv_data *ipd)
{
	int ret, io_irq;

	io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
			      PCI_INTERRUPT_INTB);
	ret = ioc3_irq_domain_setup(ipd, io_irq);
	if (ret)
		return ret;

	ret = ioc3_eth_setup(ipd);
	if (ret)
		return ret;

	ret = ioc3_serial_setup(ipd);
	if (ret)
		return ret;

	return ioc3_m48t35_setup(ipd);
}

static int ip27_baseio6g_setup(struct ioc3_priv_data *ipd)
{
	int ret, io_irq;

	io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
			      PCI_INTERRUPT_INTB);
	ret = ioc3_irq_domain_setup(ipd, io_irq);
	if (ret)
		return ret;

	ret = ioc3_eth_setup(ipd);
	if (ret)
		return ret;

	ret = ioc3_serial_setup(ipd);
	if (ret)
		return ret;

	ret = ioc3_m48t35_setup(ipd);
	if (ret)
		return ret;

	return ioc3_kbd_setup(ipd);
}

static int ip27_mio_setup(struct ioc3_priv_data *ipd)
{
	int ret;

	ret = ioc3_irq_domain_setup(ipd, ipd->pdev->irq);
	if (ret)
		return ret;

	ret = ioc3_serial_setup(ipd);
	if (ret)
		return ret;

	return ioc3_kbd_setup(ipd);
}

static int ip30_sysboard_setup(struct ioc3_priv_data *ipd)
{
	int ret, io_irq;

	io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
			      PCI_INTERRUPT_INTB);
	ret = ioc3_irq_domain_setup(ipd, io_irq);
	if (ret)
		return ret;

	ret = ioc3_eth_setup(ipd);
	if (ret)
		return ret;

	ret = ioc3_serial_setup(ipd);
	if (ret)
		return ret;

	ret = ioc3_kbd_setup(ipd);
	if (ret)
		return ret;

	ret = ioc3_ds1685_setup(ipd);
	if (ret)
		return ret;

	return ioc3_led_setup(ipd);
}

static int ioc3_menet_setup(struct ioc3_priv_data *ipd)
{
	int ret, io_irq;

	io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
			      PCI_INTERRUPT_INTB);
	ret = ioc3_irq_domain_setup(ipd, io_irq);
	if (ret)
		return ret;

	ret = ioc3_eth_setup(ipd);
	if (ret)
		return ret;

	return ioc3_serial_setup(ipd);
}

static int ioc3_menet4_setup(struct ioc3_priv_data *ipd)
{
	return ioc3_eth_setup(ipd);
}

static int ioc3_cad_duo_setup(struct ioc3_priv_data *ipd)
{
	int ret, io_irq;

	io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
			      PCI_INTERRUPT_INTB);
	ret = ioc3_irq_domain_setup(ipd, io_irq);
	if (ret)
		return ret;

	ret = ioc3_eth_setup(ipd);
	if (ret)
		return ret;

	return ioc3_kbd_setup(ipd);
}

/* Helper macro for filling ioc3_info array */
#define IOC3_SID(_name, _sid, _setup) \
	{								   \
		.name = _name,						   \
		.sid = PCI_VENDOR_ID_SGI | (IOC3_SUBSYS_ ## _sid << 16),   \
		.setup = _setup,					   \
	}

static struct {
	const char *name;
	u32 sid;
	int (*setup)(struct ioc3_priv_data *ipd);
} ioc3_infos[] = {
	IOC3_SID("IP27 BaseIO6G", IP27_BASEIO6G, &ip27_baseio6g_setup),
	IOC3_SID("IP27 MIO", IP27_MIO, &ip27_mio_setup),
	IOC3_SID("IP27 BaseIO", IP27_BASEIO, &ip27_baseio_setup),
	IOC3_SID("IP29 System Board", IP29_SYSBOARD, &ip27_baseio6g_setup),
	IOC3_SID("IP30 System Board", IP30_SYSBOARD, &ip30_sysboard_setup),
	IOC3_SID("MENET", MENET, &ioc3_menet_setup),
	IOC3_SID("MENET4", MENET4, &ioc3_menet4_setup)
};
#undef IOC3_SID

static int ioc3_setup(struct ioc3_priv_data *ipd)
{
	u32 sid;
	int i;

	/* Clear IRQs */
	writel(~0, &ipd->regs->sio_iec);
	writel(~0, &ipd->regs->sio_ir);
	writel(0, &ipd->regs->eth.eier);
	writel(~0, &ipd->regs->eth.eisr);

	/* Read subsystem vendor id and subsystem id */
	pci_read_config_dword(ipd->pdev, PCI_SUBSYSTEM_VENDOR_ID, &sid);

	for (i = 0; i < ARRAY_SIZE(ioc3_infos); i++)
		if (sid == ioc3_infos[i].sid) {
			pr_info("ioc3: %s\n", ioc3_infos[i].name);
			return ioc3_infos[i].setup(ipd);
		}

	/* Treat everything not identified by PCI subid as CAD DUO */
	pr_info("ioc3: CAD DUO\n");
	return ioc3_cad_duo_setup(ipd);
}

static int ioc3_mfd_probe(struct pci_dev *pdev,
			  const struct pci_device_id *pci_id)
{
	struct ioc3_priv_data *ipd;
	struct ioc3 __iomem *regs;
	int ret;

	ret = pci_enable_device(pdev);
	if (ret)
		return ret;

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, IOC3_LATENCY);
	pci_set_master(pdev);

	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
	if (ret) {
		pr_err("%s: No usable DMA configuration, aborting.\n",
		       pci_name(pdev));
		goto out_disable_device;
	}

	/* Set up per-IOC3 data */
	ipd = devm_kzalloc(&pdev->dev, sizeof(struct ioc3_priv_data),
			   GFP_KERNEL);
	if (!ipd) {
		ret = -ENOMEM;
		goto out_disable_device;
	}
	ipd->pdev = pdev;

	/*
	 * Map all IOC3 registers.  These are shared between subdevices
	 * so the main IOC3 module manages them.
	 */
	regs = pci_ioremap_bar(pdev, 0);
	if (!regs) {
		dev_warn(&pdev->dev, "ioc3: Unable to remap PCI BAR for %s.\n",
			 pci_name(pdev));
		ret = -ENOMEM;
		goto out_disable_device;
	}
	ipd->regs = regs;

	/* Track PCI-device specific data */
	pci_set_drvdata(pdev, ipd);

	ret = ioc3_setup(ipd);
	if (ret) {
		/* Remove all already added MFD devices */
		mfd_remove_devices(&ipd->pdev->dev);
		if (ipd->domain) {
			struct fwnode_handle *fn = ipd->domain->fwnode;

			irq_domain_remove(ipd->domain);
			irq_domain_free_fwnode(fn);
			free_irq(ipd->domain_irq, (void *)ipd);
		}
		pci_iounmap(pdev, regs);
		goto out_disable_device;
	}

	return 0;

out_disable_device:
	pci_disable_device(pdev);
	return ret;
}

static void ioc3_mfd_remove(struct pci_dev *pdev)
{
	struct ioc3_priv_data *ipd;

	ipd = pci_get_drvdata(pdev);

	/* Clear and disable all IRQs */
	writel(~0, &ipd->regs->sio_iec);
	writel(~0, &ipd->regs->sio_ir);

	/* Release resources */
	mfd_remove_devices(&ipd->pdev->dev);
	if (ipd->domain) {
		struct fwnode_handle *fn = ipd->domain->fwnode;

		irq_domain_remove(ipd->domain);
		irq_domain_free_fwnode(fn);
		free_irq(ipd->domain_irq, (void *)ipd);
	}
	pci_iounmap(pdev, ipd->regs);
	pci_disable_device(pdev);
}

static struct pci_device_id ioc3_mfd_id_table[] = {
	{ PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, ioc3_mfd_id_table);

static struct pci_driver ioc3_mfd_driver = {
	.name = "IOC3",
	.id_table = ioc3_mfd_id_table,
	.probe = ioc3_mfd_probe,
	.remove = ioc3_mfd_remove,
};

module_pci_driver(ioc3_mfd_driver);

MODULE_AUTHOR("Thomas Bogendoerfer <tbogendoerfer@suse.de>");
MODULE_DESCRIPTION("SGI IOC3 MFD driver");
MODULE_LICENSE("GPL v2");