summaryrefslogtreecommitdiffstats
path: root/drivers/media/dvb-frontends/ts2020.c
blob: 234607b02edb7707d2d56a4e44ee04c4e99a3709 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
// SPDX-License-Identifier: GPL-2.0-or-later
/*
    Montage Technology TS2020 - Silicon Tuner driver
    Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>

    Copyright (C) 2009-2012 TurboSight.com

 */

#include <media/dvb_frontend.h>
#include "ts2020.h"
#include <linux/regmap.h>
#include <linux/math64.h>

#define TS2020_XTAL_FREQ   27000 /* in kHz */
#define FREQ_OFFSET_LOW_SYM_RATE 3000

struct ts2020_priv {
	struct i2c_client *client;
	struct mutex regmap_mutex;
	struct regmap_config regmap_config;
	struct regmap *regmap;
	struct dvb_frontend *fe;
	struct delayed_work stat_work;
	int (*get_agc_pwm)(struct dvb_frontend *fe, u8 *_agc_pwm);
	/* i2c details */
	struct i2c_adapter *i2c;
	int i2c_address;
	bool loop_through:1;
	u8 clk_out:2;
	u8 clk_out_div:5;
	bool dont_poll:1;
	u32 frequency_div; /* LO output divider switch frequency */
	u32 frequency_khz; /* actual used LO frequency */
#define TS2020_M88TS2020 0
#define TS2020_M88TS2022 1
	u8 tuner;
};

struct ts2020_reg_val {
	u8 reg;
	u8 val;
};

static void ts2020_stat_work(struct work_struct *work);

static void ts2020_release(struct dvb_frontend *fe)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	struct i2c_client *client = priv->client;

	dev_dbg(&client->dev, "\n");

	i2c_unregister_device(client);
}

static int ts2020_sleep(struct dvb_frontend *fe)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	int ret;
	u8 u8tmp;

	if (priv->tuner == TS2020_M88TS2020)
		u8tmp = 0x0a; /* XXX: probably wrong */
	else
		u8tmp = 0x00;

	ret = regmap_write(priv->regmap, u8tmp, 0x00);
	if (ret < 0)
		return ret;

	/* stop statistics polling */
	if (!priv->dont_poll)
		cancel_delayed_work_sync(&priv->stat_work);
	return 0;
}

static int ts2020_init(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	struct ts2020_priv *priv = fe->tuner_priv;
	int i;
	u8 u8tmp;

	if (priv->tuner == TS2020_M88TS2020) {
		regmap_write(priv->regmap, 0x42, 0x73);
		regmap_write(priv->regmap, 0x05, priv->clk_out_div);
		regmap_write(priv->regmap, 0x20, 0x27);
		regmap_write(priv->regmap, 0x07, 0x02);
		regmap_write(priv->regmap, 0x11, 0xff);
		regmap_write(priv->regmap, 0x60, 0xf9);
		regmap_write(priv->regmap, 0x08, 0x01);
		regmap_write(priv->regmap, 0x00, 0x41);
	} else {
		static const struct ts2020_reg_val reg_vals[] = {
			{0x7d, 0x9d},
			{0x7c, 0x9a},
			{0x7a, 0x76},
			{0x3b, 0x01},
			{0x63, 0x88},
			{0x61, 0x85},
			{0x22, 0x30},
			{0x30, 0x40},
			{0x20, 0x23},
			{0x24, 0x02},
			{0x12, 0xa0},
		};

		regmap_write(priv->regmap, 0x00, 0x01);
		regmap_write(priv->regmap, 0x00, 0x03);

		switch (priv->clk_out) {
		case TS2020_CLK_OUT_DISABLED:
			u8tmp = 0x60;
			break;
		case TS2020_CLK_OUT_ENABLED:
			u8tmp = 0x70;
			regmap_write(priv->regmap, 0x05, priv->clk_out_div);
			break;
		case TS2020_CLK_OUT_ENABLED_XTALOUT:
			u8tmp = 0x6c;
			break;
		default:
			u8tmp = 0x60;
			break;
		}

		regmap_write(priv->regmap, 0x42, u8tmp);

		if (priv->loop_through)
			u8tmp = 0xec;
		else
			u8tmp = 0x6c;

		regmap_write(priv->regmap, 0x62, u8tmp);

		for (i = 0; i < ARRAY_SIZE(reg_vals); i++)
			regmap_write(priv->regmap, reg_vals[i].reg,
				     reg_vals[i].val);
	}

	/* Initialise v5 stats here */
	c->strength.len = 1;
	c->strength.stat[0].scale = FE_SCALE_DECIBEL;
	c->strength.stat[0].uvalue = 0;

	/* Start statistics polling by invoking the work function */
	ts2020_stat_work(&priv->stat_work.work);
	return 0;
}

static int ts2020_tuner_gate_ctrl(struct dvb_frontend *fe, u8 offset)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	int ret;
	ret = regmap_write(priv->regmap, 0x51, 0x1f - offset);
	ret |= regmap_write(priv->regmap, 0x51, 0x1f);
	ret |= regmap_write(priv->regmap, 0x50, offset);
	ret |= regmap_write(priv->regmap, 0x50, 0x00);
	msleep(20);
	return ret;
}

static int ts2020_set_tuner_rf(struct dvb_frontend *fe)
{
	struct ts2020_priv *dev = fe->tuner_priv;
	int ret;
	unsigned int utmp;

	ret = regmap_read(dev->regmap, 0x3d, &utmp);
	if (ret)
		return ret;

	utmp &= 0x7f;
	if (utmp < 0x16)
		utmp = 0xa1;
	else if (utmp == 0x16)
		utmp = 0x99;
	else
		utmp = 0xf9;

	regmap_write(dev->regmap, 0x60, utmp);
	ret = ts2020_tuner_gate_ctrl(fe, 0x08);

	return ret;
}

static int ts2020_set_params(struct dvb_frontend *fe)
{
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	struct ts2020_priv *priv = fe->tuner_priv;
	int ret;
	unsigned int utmp;
	u32 f3db, gdiv28;
	u16 u16tmp, value, lpf_coeff;
	u8 buf[3], reg10, lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
	unsigned int f_ref_khz, f_vco_khz, div_ref, div_out, pll_n;
	unsigned int frequency_khz = c->frequency;

	/*
	 * Integer-N PLL synthesizer
	 * kHz is used for all calculations to keep calculations within 32-bit
	 */
	f_ref_khz = TS2020_XTAL_FREQ;
	div_ref = DIV_ROUND_CLOSEST(f_ref_khz, 2000);

	/* select LO output divider */
	if (frequency_khz < priv->frequency_div) {
		div_out = 4;
		reg10 = 0x10;
	} else {
		div_out = 2;
		reg10 = 0x00;
	}

	f_vco_khz = frequency_khz * div_out;
	pll_n = f_vco_khz * div_ref / f_ref_khz;
	pll_n += pll_n % 2;
	priv->frequency_khz = pll_n * f_ref_khz / div_ref / div_out;

	pr_debug("frequency=%u offset=%d f_vco_khz=%u pll_n=%u div_ref=%u div_out=%u\n",
		 priv->frequency_khz, priv->frequency_khz - c->frequency,
		 f_vco_khz, pll_n, div_ref, div_out);

	if (priv->tuner == TS2020_M88TS2020) {
		lpf_coeff = 2766;
		reg10 |= 0x01;
		ret = regmap_write(priv->regmap, 0x10, reg10);
	} else {
		lpf_coeff = 3200;
		reg10 |= 0x0b;
		ret = regmap_write(priv->regmap, 0x10, reg10);
		ret |= regmap_write(priv->regmap, 0x11, 0x40);
	}

	u16tmp = pll_n - 1024;
	buf[0] = (u16tmp >> 8) & 0xff;
	buf[1] = (u16tmp >> 0) & 0xff;
	buf[2] = div_ref - 8;

	ret |= regmap_write(priv->regmap, 0x01, buf[0]);
	ret |= regmap_write(priv->regmap, 0x02, buf[1]);
	ret |= regmap_write(priv->regmap, 0x03, buf[2]);

	ret |= ts2020_tuner_gate_ctrl(fe, 0x10);
	if (ret < 0)
		return -ENODEV;

	ret |= ts2020_tuner_gate_ctrl(fe, 0x08);

	/* Tuner RF */
	if (priv->tuner == TS2020_M88TS2020)
		ret |= ts2020_set_tuner_rf(fe);

	gdiv28 = (TS2020_XTAL_FREQ / 1000 * 1694 + 500) / 1000;
	ret |= regmap_write(priv->regmap, 0x04, gdiv28 & 0xff);
	ret |= ts2020_tuner_gate_ctrl(fe, 0x04);
	if (ret < 0)
		return -ENODEV;

	if (priv->tuner == TS2020_M88TS2022) {
		ret = regmap_write(priv->regmap, 0x25, 0x00);
		ret |= regmap_write(priv->regmap, 0x27, 0x70);
		ret |= regmap_write(priv->regmap, 0x41, 0x09);
		ret |= regmap_write(priv->regmap, 0x08, 0x0b);
		if (ret < 0)
			return -ENODEV;
	}

	regmap_read(priv->regmap, 0x26, &utmp);
	value = utmp;

	f3db = (c->bandwidth_hz / 1000 / 2) + 2000;
	f3db += FREQ_OFFSET_LOW_SYM_RATE; /* FIXME: ~always too wide filter */
	f3db = clamp(f3db, 7000U, 40000U);

	gdiv28 = gdiv28 * 207 / (value * 2 + 151);
	mlpf_max = gdiv28 * 135 / 100;
	mlpf_min = gdiv28 * 78 / 100;
	if (mlpf_max > 63)
		mlpf_max = 63;

	nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
		(TS2020_XTAL_FREQ / 1000)  + 1) / 2;
	if (nlpf > 23)
		nlpf = 23;
	if (nlpf < 1)
		nlpf = 1;

	lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
		* lpf_coeff * 2  / f3db + 1) / 2;

	if (lpf_mxdiv < mlpf_min) {
		nlpf++;
		lpf_mxdiv = (nlpf * (TS2020_XTAL_FREQ / 1000)
			* lpf_coeff * 2  / f3db + 1) / 2;
	}

	if (lpf_mxdiv > mlpf_max)
		lpf_mxdiv = mlpf_max;

	ret = regmap_write(priv->regmap, 0x04, lpf_mxdiv);
	ret |= regmap_write(priv->regmap, 0x06, nlpf);

	ret |= ts2020_tuner_gate_ctrl(fe, 0x04);

	ret |= ts2020_tuner_gate_ctrl(fe, 0x01);

	msleep(80);

	return (ret < 0) ? -EINVAL : 0;
}

static int ts2020_get_frequency(struct dvb_frontend *fe, u32 *frequency)
{
	struct ts2020_priv *priv = fe->tuner_priv;

	*frequency = priv->frequency_khz;
	return 0;
}

static int ts2020_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
{
	*frequency = 0; /* Zero-IF */
	return 0;
}

/*
 * Get the tuner gain.
 * @fe: The front end for which we're determining the gain
 * @v_agc: The voltage of the AGC from the demodulator (0-2600mV)
 * @_gain: Where to store the gain (in 0.001dB units)
 *
 * Returns 0 or a negative error code.
 */
static int ts2020_read_tuner_gain(struct dvb_frontend *fe, unsigned v_agc,
				  __s64 *_gain)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	unsigned long gain1, gain2, gain3;
	unsigned utmp;
	int ret;

	/* Read the RF gain */
	ret = regmap_read(priv->regmap, 0x3d, &utmp);
	if (ret < 0)
		return ret;
	gain1 = utmp & 0x1f;

	/* Read the baseband gain */
	ret = regmap_read(priv->regmap, 0x21, &utmp);
	if (ret < 0)
		return ret;
	gain2 = utmp & 0x1f;

	switch (priv->tuner) {
	case TS2020_M88TS2020:
		gain1 = clamp_t(long, gain1, 0, 15);
		gain2 = clamp_t(long, gain2, 0, 13);
		v_agc = clamp_t(long, v_agc, 400, 1100);

		*_gain = -((__s64)gain1 * 2330 +
			   gain2 * 3500 +
			   v_agc * 24 / 10 * 10 +
			   10000);
		/* gain in range -19600 to -116850 in units of 0.001dB */
		break;

	case TS2020_M88TS2022:
		ret = regmap_read(priv->regmap, 0x66, &utmp);
		if (ret < 0)
			return ret;
		gain3 = (utmp >> 3) & 0x07;

		gain1 = clamp_t(long, gain1, 0, 15);
		gain2 = clamp_t(long, gain2, 2, 16);
		gain3 = clamp_t(long, gain3, 0, 6);
		v_agc = clamp_t(long, v_agc, 600, 1600);

		*_gain = -((__s64)gain1 * 2650 +
			   gain2 * 3380 +
			   gain3 * 2850 +
			   v_agc * 176 / 100 * 10 -
			   30000);
		/* gain in range -47320 to -158950 in units of 0.001dB */
		break;
	}

	return 0;
}

/*
 * Get the AGC information from the demodulator and use that to calculate the
 * tuner gain.
 */
static int ts2020_get_tuner_gain(struct dvb_frontend *fe, __s64 *_gain)
{
	struct ts2020_priv *priv = fe->tuner_priv;
	int v_agc = 0, ret;
	u8 agc_pwm;

	/* Read the AGC PWM rate from the demodulator */
	if (priv->get_agc_pwm) {
		ret = priv->get_agc_pwm(fe, &agc_pwm);
		if (ret < 0)
			return ret;

		switch (priv->tuner) {
		case TS2020_M88TS2020:
			v_agc = (int)agc_pwm * 20 - 1166;
			break;
		case TS2020_M88TS2022:
			v_agc = (int)agc_pwm * 16 - 670;
			break;
		}

		if (v_agc < 0)
			v_agc = 0;
	}

	return ts2020_read_tuner_gain(fe, v_agc, _gain);
}

/*
 * Gather statistics on a regular basis
 */
static void ts2020_stat_work(struct work_struct *work)
{
	struct ts2020_priv *priv = container_of(work, struct ts2020_priv,
					       stat_work.work);
	struct i2c_client *client = priv->client;
	struct dtv_frontend_properties *c = &priv->fe->dtv_property_cache;
	int ret;

	dev_dbg(&client->dev, "\n");

	ret = ts2020_get_tuner_gain(priv->fe, &c->strength.stat[0].svalue);
	if (ret < 0)
		goto err;

	c->strength.stat[0].scale = FE_SCALE_DECIBEL;

	if (!priv->dont_poll)
		schedule_delayed_work(&priv->stat_work, msecs_to_jiffies(2000));
	return;
err:
	dev_dbg(&client->dev, "failed=%d\n", ret);
}

/*
 * Read TS2020 signal strength in v3 format.
 */
static int ts2020_read_signal_strength(struct dvb_frontend *fe,
				       u16 *_signal_strength)
{
	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
	struct ts2020_priv *priv = fe->tuner_priv;
	unsigned strength;
	__s64 gain;

	if (priv->dont_poll)
		ts2020_stat_work(&priv->stat_work.work);

	if (c->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
		*_signal_strength = 0;
		return 0;
	}

	gain = c->strength.stat[0].svalue;

	/* Calculate the signal strength based on the total gain of the tuner */
	if (gain < -85000)
		/* 0%: no signal or weak signal */
		strength = 0;
	else if (gain < -65000)
		/* 0% - 60%: weak signal */
		strength = 0 + div64_s64((85000 + gain) * 3, 1000);
	else if (gain < -45000)
		/* 60% - 90%: normal signal */
		strength = 60 + div64_s64((65000 + gain) * 3, 2000);
	else
		/* 90% - 99%: strong signal */
		strength = 90 + div64_s64((45000 + gain), 5000);

	*_signal_strength = strength * 65535 / 100;
	return 0;
}

static const struct dvb_tuner_ops ts2020_tuner_ops = {
	.info = {
		.name = "TS2020",
		.frequency_min_hz =  950 * MHz,
		.frequency_max_hz = 2150 * MHz
	},
	.init = ts2020_init,
	.release = ts2020_release,
	.sleep = ts2020_sleep,
	.set_params = ts2020_set_params,
	.get_frequency = ts2020_get_frequency,
	.get_if_frequency = ts2020_get_if_frequency,
	.get_rf_strength = ts2020_read_signal_strength,
};

struct dvb_frontend *ts2020_attach(struct dvb_frontend *fe,
					const struct ts2020_config *config,
					struct i2c_adapter *i2c)
{
	struct i2c_client *client;
	struct i2c_board_info board_info;

	/* This is only used by ts2020_probe() so can be on the stack */
	struct ts2020_config pdata;

	memcpy(&pdata, config, sizeof(pdata));
	pdata.fe = fe;
	pdata.attach_in_use = true;

	memset(&board_info, 0, sizeof(board_info));
	strscpy(board_info.type, "ts2020", I2C_NAME_SIZE);
	board_info.addr = config->tuner_address;
	board_info.platform_data = &pdata;
	client = i2c_new_client_device(i2c, &board_info);
	if (!i2c_client_has_driver(client))
		return NULL;

	return fe;
}
EXPORT_SYMBOL(ts2020_attach);

/*
 * We implement own regmap locking due to legacy DVB attach which uses frontend
 * gate control callback to control I2C bus access. We can open / close gate and
 * serialize whole open / I2C-operation / close sequence at the same.
 */
static void ts2020_regmap_lock(void *__dev)
{
	struct ts2020_priv *dev = __dev;

	mutex_lock(&dev->regmap_mutex);
	if (dev->fe->ops.i2c_gate_ctrl)
		dev->fe->ops.i2c_gate_ctrl(dev->fe, 1);
}

static void ts2020_regmap_unlock(void *__dev)
{
	struct ts2020_priv *dev = __dev;

	if (dev->fe->ops.i2c_gate_ctrl)
		dev->fe->ops.i2c_gate_ctrl(dev->fe, 0);
	mutex_unlock(&dev->regmap_mutex);
}

static int ts2020_probe(struct i2c_client *client,
		const struct i2c_device_id *id)
{
	struct ts2020_config *pdata = client->dev.platform_data;
	struct dvb_frontend *fe = pdata->fe;
	struct ts2020_priv *dev;
	int ret;
	u8 u8tmp;
	unsigned int utmp;
	char *chip_str;

	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	if (!dev) {
		ret = -ENOMEM;
		goto err;
	}

	/* create regmap */
	mutex_init(&dev->regmap_mutex);
	dev->regmap_config.reg_bits = 8,
	dev->regmap_config.val_bits = 8,
	dev->regmap_config.lock = ts2020_regmap_lock,
	dev->regmap_config.unlock = ts2020_regmap_unlock,
	dev->regmap_config.lock_arg = dev,
	dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
	if (IS_ERR(dev->regmap)) {
		ret = PTR_ERR(dev->regmap);
		goto err_kfree;
	}

	dev->i2c = client->adapter;
	dev->i2c_address = client->addr;
	dev->loop_through = pdata->loop_through;
	dev->clk_out = pdata->clk_out;
	dev->clk_out_div = pdata->clk_out_div;
	dev->dont_poll = pdata->dont_poll;
	dev->frequency_div = pdata->frequency_div;
	dev->fe = fe;
	dev->get_agc_pwm = pdata->get_agc_pwm;
	fe->tuner_priv = dev;
	dev->client = client;
	INIT_DELAYED_WORK(&dev->stat_work, ts2020_stat_work);

	/* check if the tuner is there */
	ret = regmap_read(dev->regmap, 0x00, &utmp);
	if (ret)
		goto err_regmap_exit;

	if ((utmp & 0x03) == 0x00) {
		ret = regmap_write(dev->regmap, 0x00, 0x01);
		if (ret)
			goto err_regmap_exit;

		usleep_range(2000, 50000);
	}

	ret = regmap_write(dev->regmap, 0x00, 0x03);
	if (ret)
		goto err_regmap_exit;

	usleep_range(2000, 50000);

	ret = regmap_read(dev->regmap, 0x00, &utmp);
	if (ret)
		goto err_regmap_exit;

	dev_dbg(&client->dev, "chip_id=%02x\n", utmp);

	switch (utmp) {
	case 0x01:
	case 0x41:
	case 0x81:
		dev->tuner = TS2020_M88TS2020;
		chip_str = "TS2020";
		if (!dev->frequency_div)
			dev->frequency_div = 1060000;
		break;
	case 0xc3:
	case 0x83:
		dev->tuner = TS2020_M88TS2022;
		chip_str = "TS2022";
		if (!dev->frequency_div)
			dev->frequency_div = 1103000;
		break;
	default:
		ret = -ENODEV;
		goto err_regmap_exit;
	}

	if (dev->tuner == TS2020_M88TS2022) {
		switch (dev->clk_out) {
		case TS2020_CLK_OUT_DISABLED:
			u8tmp = 0x60;
			break;
		case TS2020_CLK_OUT_ENABLED:
			u8tmp = 0x70;
			ret = regmap_write(dev->regmap, 0x05, dev->clk_out_div);
			if (ret)
				goto err_regmap_exit;
			break;
		case TS2020_CLK_OUT_ENABLED_XTALOUT:
			u8tmp = 0x6c;
			break;
		default:
			ret = -EINVAL;
			goto err_regmap_exit;
		}

		ret = regmap_write(dev->regmap, 0x42, u8tmp);
		if (ret)
			goto err_regmap_exit;

		if (dev->loop_through)
			u8tmp = 0xec;
		else
			u8tmp = 0x6c;

		ret = regmap_write(dev->regmap, 0x62, u8tmp);
		if (ret)
			goto err_regmap_exit;
	}

	/* sleep */
	ret = regmap_write(dev->regmap, 0x00, 0x00);
	if (ret)
		goto err_regmap_exit;

	dev_info(&client->dev,
		 "Montage Technology %s successfully identified\n", chip_str);

	memcpy(&fe->ops.tuner_ops, &ts2020_tuner_ops,
			sizeof(struct dvb_tuner_ops));
	if (!pdata->attach_in_use)
		fe->ops.tuner_ops.release = NULL;

	i2c_set_clientdata(client, dev);
	return 0;
err_regmap_exit:
	regmap_exit(dev->regmap);
err_kfree:
	kfree(dev);
err:
	dev_dbg(&client->dev, "failed=%d\n", ret);
	return ret;
}

static int ts2020_remove(struct i2c_client *client)
{
	struct ts2020_priv *dev = i2c_get_clientdata(client);

	dev_dbg(&client->dev, "\n");

	/* stop statistics polling */
	if (!dev->dont_poll)
		cancel_delayed_work_sync(&dev->stat_work);

	regmap_exit(dev->regmap);
	kfree(dev);
	return 0;
}

static const struct i2c_device_id ts2020_id_table[] = {
	{"ts2020", 0},
	{"ts2022", 0},
	{}
};
MODULE_DEVICE_TABLE(i2c, ts2020_id_table);

static struct i2c_driver ts2020_driver = {
	.driver = {
		.name	= "ts2020",
	},
	.probe		= ts2020_probe,
	.remove		= ts2020_remove,
	.id_table	= ts2020_id_table,
};

module_i2c_driver(ts2020_driver);

MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
MODULE_DESCRIPTION("Montage Technology TS2020 - Silicon tuner driver module");
MODULE_LICENSE("GPL");