summaryrefslogtreecommitdiffstats
path: root/drivers/clk/sunxi-ng/ccu_nm.h
blob: de232f2199a6ba3982670001062571ad12e0fa83 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
/*
 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _CCU_NM_H_
#define _CCU_NM_H_

#include <linux/clk-provider.h>

#include "ccu_common.h"
#include "ccu_div.h"
#include "ccu_frac.h"
#include "ccu_mult.h"
#include "ccu_sdm.h"

/*
 * struct ccu_nm - Definition of an N-M clock
 *
 * Clocks based on the formula parent * N / M
 */
struct ccu_nm {
	u32			enable;
	u32			lock;

	struct ccu_mult_internal	n;
	struct ccu_div_internal		m;
	struct ccu_frac_internal	frac;
	struct ccu_sdm_internal		sdm;

	unsigned int		fixed_post_div;
	unsigned int		min_rate;
	unsigned int		max_rate;

	struct ccu_common	common;
};

#define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg,	\
					_nshift, _nwidth,		\
					_mshift, _mwidth,		\
					_sdm_table, _sdm_en,		\
					_sdm_reg, _sdm_reg_en,		\
					_gate, _lock, _flags)		\
	struct ccu_nm _struct = {					\
		.enable		= _gate,				\
		.lock		= _lock,				\
		.n		= _SUNXI_CCU_MULT(_nshift, _nwidth),	\
		.m		= _SUNXI_CCU_DIV(_mshift, _mwidth),	\
		.sdm		= _SUNXI_CCU_SDM(_sdm_table, _sdm_en,	\
						 _sdm_reg, _sdm_reg_en),\
		.common		= {					\
			.reg		= _reg,				\
			.features	= CCU_FEATURE_SIGMA_DELTA_MOD,	\
			.hw.init	= CLK_HW_INIT(_name,		\
						      _parent,		\
						      &ccu_nm_ops,	\
						      _flags),		\
		},							\
	}

#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg,	\
					 _nshift, _nwidth,		\
					 _mshift, _mwidth,		\
					 _frac_en, _frac_sel,		\
					 _frac_rate_0, _frac_rate_1,	\
					 _gate, _lock, _flags)		\
	struct ccu_nm _struct = {					\
		.enable		= _gate,				\
		.lock		= _lock,				\
		.n		= _SUNXI_CCU_MULT(_nshift, _nwidth),	\
		.m		= _SUNXI_CCU_DIV(_mshift, _mwidth),	\
		.frac		= _SUNXI_CCU_FRAC(_frac_en, _frac_sel,	\
						  _frac_rate_0,		\
						  _frac_rate_1),	\
		.common		= {					\
			.reg		= _reg,				\
			.features	= CCU_FEATURE_FRACTIONAL,	\
			.hw.init	= CLK_HW_INIT(_name,		\
						      _parent,		\
						      &ccu_nm_ops,	\
						      _flags),		\
		},							\
	}

#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent,	\
					     _reg, _min_rate,		\
					     _nshift, _nwidth,		\
					     _mshift, _mwidth,		\
					     _frac_en, _frac_sel,	\
					     _frac_rate_0, _frac_rate_1,\
					     _gate, _lock, _flags)	\
	struct ccu_nm _struct = {					\
		.enable		= _gate,				\
		.lock		= _lock,				\
		.n		= _SUNXI_CCU_MULT(_nshift, _nwidth),	\
		.m		= _SUNXI_CCU_DIV(_mshift, _mwidth),	\
		.frac		= _SUNXI_CCU_FRAC(_frac_en, _frac_sel,	\
						  _frac_rate_0,		\
						  _frac_rate_1),	\
		.min_rate	= _min_rate,				\
		.common		= {					\
			.reg		= _reg,				\
			.features	= CCU_FEATURE_FRACTIONAL,	\
			.hw.init	= CLK_HW_INIT(_name,		\
						      _parent,		\
						      &ccu_nm_ops,	\
						      _flags),		\
		},							\
	}

#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name,	\
						 _parent, _reg,		\
						 _min_rate, _max_rate,	\
						 _nshift, _nwidth,	\
						 _mshift, _mwidth,	\
						 _frac_en, _frac_sel,	\
						 _frac_rate_0,		\
						 _frac_rate_1,		\
						 _gate, _lock, _flags)	\
	struct ccu_nm _struct = {					\
		.enable		= _gate,				\
		.lock		= _lock,				\
		.n		= _SUNXI_CCU_MULT(_nshift, _nwidth),	\
		.m		= _SUNXI_CCU_DIV(_mshift, _mwidth),	\
		.frac		= _SUNXI_CCU_FRAC(_frac_en, _frac_sel,	\
						  _frac_rate_0,		\
						  _frac_rate_1),	\
		.min_rate	= _min_rate,				\
		.max_rate	= _max_rate,				\
		.common		= {					\
			.reg		= _reg,				\
			.features	= CCU_FEATURE_FRACTIONAL,	\
			.hw.init	= CLK_HW_INIT(_name,		\
						      _parent,		\
						      &ccu_nm_ops,	\
						      _flags),		\
		},							\
	}

#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg,	\
				    _nshift, _nwidth,			\
				    _mshift, _mwidth,			\
				    _gate, _lock, _flags)		\
	struct ccu_nm _struct = {					\
		.enable		= _gate,				\
		.lock		= _lock,				\
		.n		= _SUNXI_CCU_MULT(_nshift, _nwidth),	\
		.m		= _SUNXI_CCU_DIV(_mshift, _mwidth),	\
		.common		= {					\
			.reg		= _reg,				\
			.hw.init	= CLK_HW_INIT(_name,		\
						      _parent,		\
						      &ccu_nm_ops,	\
						      _flags),		\
		},							\
	}

static inline struct ccu_nm *hw_to_ccu_nm(struct clk_hw *hw)
{
	struct ccu_common *common = hw_to_ccu_common(hw);

	return container_of(common, struct ccu_nm, common);
}

extern const struct clk_ops ccu_nm_ops;

#endif /* _CCU_NM_H_ */