summaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
blob: 61815228e230b1d96533851dcf020ca8cd83a321 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for AM6 SoC Family Main Domain peripherals
 *
 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
 */
#include <dt-bindings/phy/phy-am654-serdes.h>

&cbass_main {
	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x0 0x70000000 0x0 0x200000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x70000000 0x200000>;

		atf-sram@0 {
			reg = <0x0 0x20000>;
		};

		sysfw-sram@f0000 {
			reg = <0xf0000 0x10000>;
		};

		l3cache-sram@100000 {
			reg = <0x100000 0x100000>;
		};
	};

	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
		      <0x00 0x01880000 0x00 0x90000>;	/* GICR */
		/*
		 * vcpumntirq:
		 * virtual CPU interface maintenance interrupt
		 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: gic-its@1820000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			socionext,synquacer-pre-its = <0x1000000 0x400000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	serdes0: serdes@900000 {
		compatible = "ti,phy-am654-serdes";
		reg = <0x0 0x900000 0x0 0x2000>;
		reg-names = "serdes";
		#phy-cells = <2>;
		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
		clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
		assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
		assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
		ti,serdes-clk = <&serdes0_clk>;
		#clock-cells = <1>;
		mux-controls = <&serdes_mux 0>;
	};

	serdes1: serdes@910000 {
		compatible = "ti,phy-am654-serdes";
		reg = <0x0 0x910000 0x0 0x2000>;
		reg-names = "serdes";
		#phy-cells = <2>;
		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
		clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
		assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
		assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
		ti,serdes-clk = <&serdes1_clk>;
		#clock-cells = <1>;
		mux-controls = <&serdes_mux 1>;
	};

	main_uart0: serial@2800000 {
		compatible = "ti,am654-uart";
		reg = <0x00 0x02800000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		current-speed = <115200>;
		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart1: serial@2810000 {
		compatible = "ti,am654-uart";
		reg = <0x00 0x02810000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart2: serial@2820000 {
		compatible = "ti,am654-uart";
		reg = <0x00 0x02820000 0x00 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <48000000>;
		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
	};

	main_pmx0: pinmux@11c000 {
		compatible = "pinctrl-single";
		reg = <0x0 0x11c000 0x0 0x2e4>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	main_pmx1: pinmux@11c2e8 {
		compatible = "pinctrl-single";
		reg = <0x0 0x11c2e8 0x0 0x24>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	main_i2c0: i2c@2000000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2000000 0x0 0x100>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 110 1>;
		power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c1: i2c@2010000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2010000 0x0 0x100>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 111 1>;
		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c2: i2c@2020000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2020000 0x0 0x100>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 112 1>;
		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c3: i2c@2030000 {
		compatible = "ti,am654-i2c", "ti,omap4-i2c";
		reg = <0x0 0x2030000 0x0 0x100>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "fck";
		clocks = <&k3_clks 113 1>;
		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
	};

	ecap0: pwm@3100000 {
		compatible = "ti,am654-ecap", "ti,am3352-ecap";
		#pwm-cells = <3>;
		reg = <0x0 0x03100000 0x0 0x60>;
		power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 39 0>;
		clock-names = "fck";
	};

	main_spi0: spi@2100000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2100000 0x0 0x400>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 137 1>;
		power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
		dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
		dma-names = "tx0", "rx0";
	};

	main_spi1: spi@2110000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2110000 0x0 0x400>;
		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 138 1>;
		power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
		assigned-clocks = <&k3_clks 137 1>;
		assigned-clock-rates = <48000000>;
	};

	main_spi2: spi@2120000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2120000 0x0 0x400>;
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 139 1>;
		power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	main_spi3: spi@2130000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2130000 0x0 0x400>;
		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 140 1>;
		power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	main_spi4: spi@2140000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x0 0x2140000 0x0 0x400>;
		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 141 1>;
		power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	sdhci0: sdhci@4f80000 {
		compatible = "ti,am654-sdhci-5.1";
		reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
		power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
		clock-names = "clk_ahb", "clk_xin";
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		ti,otap-del-sel = <0x2>;
		ti,trm-icp = <0x8>;
		dma-coherent;
	};

	scm_conf: scm_conf@100000 {
		compatible = "syscon", "simple-mfd";
		reg = <0 0x00100000 0 0x1c000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x00100000 0x1c000>;

		pcie0_mode: pcie-mode@4060 {
			compatible = "syscon";
			reg = <0x00004060 0x4>;
		};

		pcie1_mode: pcie-mode@4070 {
			compatible = "syscon";
			reg = <0x00004070 0x4>;
		};

		pcie_devid: pcie-devid@210 {
			compatible = "syscon";
			reg = <0x00000210 0x4>;
		};

		serdes0_clk: serdes_clk@4080 {
			compatible = "syscon";
			reg = <0x00004080 0x4>;
		};

		serdes1_clk: serdes_clk@4090 {
			compatible = "syscon";
			reg = <0x00004090 0x4>;
		};

		serdes_mux: mux-controller {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
					<0x4090 0x3>; /* SERDES1 lane select */
		};

		dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 {
			compatible = "syscon";
			reg = <0x0000041E0 0x14>;
		};

		ehrpwm_tbclk: syscon@4140 {
			compatible = "ti,am654-ehrpwm-tbclk", "syscon";
			reg = <0x4140 0x18>;
			#clock-cells = <1>;
		};
	};

	dwc3_0: dwc3@4000000 {
		compatible = "ti,am654-dwc3";
		reg = <0x0 0x4000000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x4000000 0x20000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		dma-coherent;
		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
		assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
		assigned-clock-parents = <&k3_clks 151 4>,	/* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
					 <&k3_clks 151 9>;	/* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */

		usb0: usb@10000 {
			compatible = "snps,dwc3";
			reg = <0x10000 0x10000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "peripheral",
					  "host",
					  "otg";
			maximum-speed = "high-speed";
			dr_mode = "otg";
			phys = <&usb0_phy>;
			phy-names = "usb2-phy";
			snps,dis_u3_susphy_quirk;
		};
	};

	usb0_phy: phy@4100000 {
		compatible = "ti,am654-usb2", "ti,omap-usb2";
		reg = <0x0 0x4100000 0x0 0x54>;
		syscon-phy-power = <&scm_conf 0x4000>;
		clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
		clock-names = "wkupclk", "refclk";
		#phy-cells = <0>;
	};

	dwc3_1: dwc3@4020000 {
		compatible = "ti,am654-dwc3";
		reg = <0x0 0x4020000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x4020000 0x20000>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		dma-coherent;
		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 152 2>;
		assigned-clocks = <&k3_clks 152 2>;
		assigned-clock-parents = <&k3_clks 152 4>;	/* set REF_CLK to 20MHz i.e. PER0_PLL/48 */

		usb1: usb@10000 {
			compatible = "snps,dwc3";
			reg = <0x10000 0x10000>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "peripheral",
					  "host",
					  "otg";
			maximum-speed = "high-speed";
			dr_mode = "otg";
			phys = <&usb1_phy>;
			phy-names = "usb2-phy";
		};
	};

	usb1_phy: phy@4110000 {
		compatible = "ti,am654-usb2", "ti,omap-usb2";
		reg = <0x0 0x4110000 0x0 0x54>;
		syscon-phy-power = <&scm_conf 0x4020>;
		clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
		clock-names = "wkupclk", "refclk";
		#phy-cells = <0>;
	};

	intr_main_gpio: interrupt-controller0 {
		compatible = "ti,sci-intr";
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <2>;
		ti,sci = <&dmsc>;
		ti,sci-dst-id = <56>;
		ti,sci-rm-range-girq = <0x1>;
	};

	main_navss {
		compatible = "simple-mfd";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-coherent;
		dma-ranges;

		ti,sci-dev-id = <118>;

		intr_main_navss: interrupt-controller1 {
			compatible = "ti,sci-intr";
			ti,intr-trigger-type = <4>;
			interrupt-controller;
			interrupt-parent = <&gic500>;
			#interrupt-cells = <2>;
			ti,sci = <&dmsc>;
			ti,sci-dst-id = <56>;
			ti,sci-rm-range-girq = <0x0>, <0x2>;
		};

		inta_main_udmass: interrupt-controller@33d00000 {
			compatible = "ti,sci-inta";
			reg = <0x0 0x33d00000 0x0 0x100000>;
			interrupt-controller;
			interrupt-parent = <&intr_main_navss>;
			msi-controller;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <179>;
			ti,sci-rm-range-vint = <0x0>;
			ti,sci-rm-range-global-event = <0x1>;
		};

		secure_proxy_main: mailbox@32c00000 {
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <1>;
			reg-names = "target_data", "rt", "scfg";
			reg = <0x00 0x32c00000 0x00 0x100000>,
			      <0x00 0x32400000 0x00 0x100000>,
			      <0x00 0x32800000 0x00 0x100000>;
			interrupt-names = "rx_011";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		};

		hwspinlock: spinlock@30e00000 {
			compatible = "ti,am654-hwspinlock";
			reg = <0x00 0x30e00000 0x00 0x1000>;
			#hwlock-cells = <1>;
		};

		mailbox0_cluster0: mailbox@31f80000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f80000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster1: mailbox@31f81000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f81000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster2: mailbox@31f82000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f82000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster3: mailbox@31f83000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f83000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster4: mailbox@31f84000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f84000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster5: mailbox@31f85000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f85000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster6: mailbox@31f86000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f86000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster7: mailbox@31f87000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f87000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster8: mailbox@31f88000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f88000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster9: mailbox@31f89000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f89000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster10: mailbox@31f8a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8a000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		mailbox0_cluster11: mailbox@31f8b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8b000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&intr_main_navss>;
		};

		ringacc: ringacc@3c000000 {
			compatible = "ti,am654-navss-ringacc";
			reg =	<0x0 0x3c000000 0x0 0x400000>,
				<0x0 0x38000000 0x0 0x400000>,
				<0x0 0x31120000 0x0 0x100>,
				<0x0 0x33000000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
			ti,num-rings = <818>;
			ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
			ti,dma-ring-reset-quirk;
			ti,sci = <&dmsc>;
			ti,sci-dev-id = <187>;
			msi-parent = <&inta_main_udmass>;
		};

		main_udmap: dma-controller@31150000 {
			compatible = "ti,am654-navss-main-udmap";
			reg =	<0x0 0x31150000 0x0 0x100>,
				<0x0 0x34000000 0x0 0x100000>,
				<0x0 0x35000000 0x0 0x100000>;
			reg-names = "gcfg", "rchanrt", "tchanrt";
			msi-parent = <&inta_main_udmass>;
			#dma-cells = <1>;

			ti,sci = <&dmsc>;
			ti,sci-dev-id = <188>;
			ti,ringacc = <&ringacc>;

			ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
						<0x2>; /* TX_CHAN */
			ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
						<0x5>; /* RX_CHAN */
			ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
		};

		cpts@310d0000 {
			compatible = "ti,am65-cpts";
			reg = <0x0 0x310d0000 0x0 0x400>;
			reg-names = "cpts";
			clocks = <&main_cpts_mux>;
			clock-names = "cpts";
			interrupts-extended = <&intr_main_navss 163 0>;
			interrupt-names = "cpts";
			ti,cpts-periodic-outputs = <6>;
			ti,cpts-ext-ts-inputs = <8>;

			main_cpts_mux: refclk-mux {
				#clock-cells = <0>;
				clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
					<&k3_clks 118 6>, <&k3_clks 118 3>,
					<&k3_clks 118 8>, <&k3_clks 118 14>,
					<&k3_clks 120 3>, <&k3_clks 121 3>;
				assigned-clocks = <&main_cpts_mux>;
				assigned-clock-parents = <&k3_clks 118 5>;
			};
		};
	};

	main_gpio0:  main_gpio0@600000 {
		compatible = "ti,am654-gpio", "ti,keystone-gpio";
		reg = <0x0 0x600000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&intr_main_gpio>;
		interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
				<57 261>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <96>;
		ti,davinci-gpio-unbanked = <0>;
		clocks = <&k3_clks 57 0>;
		clock-names = "gpio";
	};

	main_gpio1:  main_gpio1@601000 {
		compatible = "ti,am654-gpio", "ti,keystone-gpio";
		reg = <0x0 0x601000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&intr_main_gpio>;
		interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
				<58 261>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <90>;
		ti,davinci-gpio-unbanked = <0>;
		clocks = <&k3_clks 58 0>;
		clock-names = "gpio";
	};

	pcie0_rc: pcie@5500000 {
		compatible = "ti,am654-pcie-rc";
		reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
		reg-names = "app", "dbics", "config", "atu";
		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
			  0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
		ti,syscon-pcie-id = <&pcie_devid>;
		ti,syscon-pcie-mode = <&pcie0_mode>;
		bus-range = <0x0 0xff>;
		num-viewport = <16>;
		max-link-speed = <3>;
		dma-coherent;
		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
		msi-map = <0x0 &gic_its 0x0 0x10000>;
	};

	pcie0_ep: pcie-ep@5500000 {
		compatible = "ti,am654-pcie-ep";
		reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
		reg-names = "app", "dbics", "addr_space", "atu";
		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
		ti,syscon-pcie-mode = <&pcie0_mode>;
		num-ib-windows = <16>;
		num-ob-windows = <16>;
		max-link-speed = <3>;
		dma-coherent;
		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
	};

	pcie1_rc: pcie@5600000 {
		compatible = "ti,am654-pcie-rc";
		reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
		reg-names = "app", "dbics", "config", "atu";
		power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
			  0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
		ti,syscon-pcie-id = <&pcie_devid>;
		ti,syscon-pcie-mode = <&pcie1_mode>;
		bus-range = <0x0 0xff>;
		num-viewport = <16>;
		max-link-speed = <3>;
		dma-coherent;
		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
		msi-map = <0x0 &gic_its 0x10000 0x10000>;
	};

	pcie1_ep: pcie-ep@5600000 {
		compatible = "ti,am654-pcie-ep";
		reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
		reg-names = "app", "dbics", "addr_space", "atu";
		power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
		ti,syscon-pcie-mode = <&pcie1_mode>;
		num-ib-windows = <16>;
		num-ob-windows = <16>;
		max-link-speed = <3>;
		dma-coherent;
		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
	};

	mcasp0: mcasp@2b00000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b00000 0x0 0x2000>,
			<0x0 0x02b08000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 104 0>;
		clock-names = "fck";
		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;

		status = "disabled";
	};

	mcasp1: mcasp@2b10000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b10000 0x0 0x2000>,
			<0x0 0x02b18000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 105 0>;
		clock-names = "fck";
		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;

		status = "disabled";
	};

	mcasp2: mcasp@2b20000 {
		compatible = "ti,am33xx-mcasp-audio";
		reg = <0x0 0x02b20000 0x0 0x2000>,
			<0x0 0x02b28000 0x0 0x1000>;
		reg-names = "mpu","dat";
		interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "tx", "rx";

		dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
		dma-names = "tx", "rx";

		clocks = <&k3_clks 106 0>;
		clock-names = "fck";
		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;

		status = "disabled";
	};

	cal: cal@6f03000 {
		compatible = "ti,am654-cal";
		reg = <0x0 0x06f03000 0x0 0x400>,
		      <0x0 0x06f03800 0x0 0x40>;
		reg-names = "cal_top",
			    "cal_rx_core0";
		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
		ti,camerrx-control = <&scm_conf 0x40c0>;
		clock-names = "fck";
		clocks = <&k3_clks 2 0>;
		power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			csi2_0: port@0 {
				reg = <0>;
			};
		};
	};

	dss: dss@04a00000 {
		compatible = "ti,am65x-dss";
		reg =	<0x0 0x04a00000 0x0 0x1000>, /* common */
			<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
			<0x0 0x04a06000 0x0 0x1000>, /* vid */
			<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
			<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
			<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
			<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
		reg-names = "common", "vidl1", "vid",
			"ovr1", "ovr2", "vp1", "vp2";

		ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;

		power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;

		clocks =	<&k3_clks 67 1>,
				<&k3_clks 216 1>,
				<&k3_clks 67 2>;
		clock-names = "fck", "vp1", "vp2";

		/*
		 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
		 * DIV1. See "Figure 12-3365. DSS Integration"
		 * in AM65x TRM for details.
		 */
		assigned-clocks = <&k3_clks 67 2>;
		assigned-clock-parents = <&k3_clks 67 5>;

		interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;

		status = "disabled";

		dss_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	ehrpwm0: pwm@3000000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3000000 0x0 0x100>;
		power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
		clock-names = "tbclk", "fck";
	};

	ehrpwm1: pwm@3010000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3010000 0x0 0x100>;
		power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
		clock-names = "tbclk", "fck";
	};

	ehrpwm2: pwm@3020000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3020000 0x0 0x100>;
		power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
		clock-names = "tbclk", "fck";
	};

	ehrpwm3: pwm@3030000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3030000 0x0 0x100>;
		power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
		clock-names = "tbclk", "fck";
	};

	ehrpwm4: pwm@3040000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3040000 0x0 0x100>;
		power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
		clock-names = "tbclk", "fck";
	};

	ehrpwm5: pwm@3050000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x0 0x3050000 0x0 0x100>;
		power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
		clock-names = "tbclk", "fck";
	};
};