blob: 79e8ce59baa8854bfdc6846dba584453701f1f08 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
* Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and
* two CP110.
*/
#include "armada-ap806-quad.dtsi"
#include "armada-80x0.dtsi"
/ {
model = "Marvell Armada 8040";
compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
"marvell,armada-ap806";
};
&smmu {
status = "okay";
};
&cp0_pcie0 {
iommu-map =
<0x0 &smmu 0x480 0x20>,
<0x100 &smmu 0x4a0 0x20>,
<0x200 &smmu 0x4c0 0x20>;
iommu-map-mask = <0x031f>;
};
/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
* in CP master is not connected (by package) to the oscillator. So
* disable it. However, the RTC clock in CP slave is connected to the
* oscillator so this one is let enabled.
*/
&cp0_rtc {
status = "disabled";
};
&cp0_sata0 {
iommus = <&smmu 0x444>;
};
&cp0_sdhci0 {
iommus = <&smmu 0x445>;
};
&cp0_usb3_0 {
iommus = <&smmu 0x440>;
};
&cp0_usb3_1 {
iommus = <&smmu 0x441>;
};
&cp1_sata0 {
iommus = <&smmu 0x454>;
};
&cp1_usb3_0 {
iommus = <&smmu 0x450>;
};
&cp1_usb3_1 {
iommus = <&smmu 0x451>;
};
|