summaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/freescale/s32g2.dtsi
blob: 824d401e7a2c5325299c8ce3b90303f4162382ac (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * NXP S32G2 SoC family
 *
 * Copyright (c) 2021 SUSE LLC
 * Copyright (c) 2017-2021 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "nxp,s32g2";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cluster0_l2: l2-cache0 {
			compatible = "cache";
		};

		cluster1_l2: l2-cache1 {
			compatible = "cache";
		};
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	firmware {
		psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0x80000000>;

		uart0: serial@401c8000 {
			compatible = "nxp,s32g2-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x401c8000 0x3000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		uart1: serial@401cc000 {
			compatible = "nxp,s32g2-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x401cc000 0x3000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		uart2: serial@402bc000 {
			compatible = "nxp,s32g2-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x402bc000 0x3000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		gic: interrupt-controller@50800000 {
			compatible = "arm,gic-v3";
			reg = <0x50800000 0x10000>,
			      <0x50880000 0x80000>,
			      <0x50400000 0x2000>,
			      <0x50410000 0x2000>,
			      <0x50420000 0x2000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};
};