1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
|
/*
* wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
*
* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
*
* Licensed under GPLv2 or later
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "wm,wm8505";
cpus {
#address-cells = <0>;
#size-cells = <0>;
cpu {
device_type = "cpu";
compatible = "arm,arm926ej-s";
};
};
memory {
device_type = "memory";
reg = <0x0 0x0>;
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
interrupt-parent = <&intc0>;
intc0: interrupt-controller@d8140000 {
compatible = "via,vt8500-intc";
interrupt-controller;
reg = <0xd8140000 0x10000>;
#interrupt-cells = <1>;
};
/* Secondary IC cascaded to intc0 */
intc1: interrupt-controller@d8150000 {
compatible = "via,vt8500-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xD8150000 0x10000>;
interrupts = <56 57 58 59 60 61 62 63>;
};
pinctrl: pinctrl@d8110000 {
compatible = "wm,wm8505-pinctrl";
reg = <0xd8110000 0x10000>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
pmc@d8130000 {
compatible = "via,vt8500-pmc";
reg = <0xd8130000 0x1000>;
clocks {
#address-cells = <1>;
#size-cells = <0>;
ref24: ref24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
ref25: ref25M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
plla: plla {
#clock-cells = <0>;
compatible = "via,vt8500-pll-clock";
clocks = <&ref25>;
reg = <0x200>;
};
pllb: pllb {
#clock-cells = <0>;
compatible = "via,vt8500-pll-clock";
clocks = <&ref25>;
reg = <0x204>;
};
pllc: pllc {
#clock-cells = <0>;
compatible = "via,vt8500-pll-clock";
clocks = <&ref25>;
reg = <0x208>;
};
plld: plld {
#clock-cells = <0>;
compatible = "via,vt8500-pll-clock";
clocks = <&ref25>;
reg = <0x20c>;
};
clkarm: arm {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&plla>;
divisor-reg = <0x300>;
};
clkahb: ahb {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x304>;
};
clkapb: apb {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x350>;
};
clkddr: ddr {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&plld>;
divisor-reg = <0x310>;
};
clkuart0: uart0 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x250>;
enable-bit = <1>;
};
clkuart1: uart1 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x250>;
enable-bit = <2>;
};
clkuart2: uart2 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x250>;
enable-bit = <3>;
};
clkuart3: uart3 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x250>;
enable-bit = <4>;
};
clkuart4: uart4 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x250>;
enable-bit = <22>;
};
clkuart5: uart5 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x250>;
enable-bit = <23>;
};
clksdhc: sdhc {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&pllb>;
divisor-reg = <0x328>;
divisor-mask = <0x3f>;
enable-reg = <0x254>;
enable-bit = <18>;
};
};
};
timer@d8130100 {
compatible = "via,vt8500-timer";
reg = <0xd8130100 0x28>;
interrupts = <36>;
};
ehci@d8007100 {
compatible = "via,vt8500-ehci";
reg = <0xd8007100 0x200>;
interrupts = <1>;
};
uhci@d8007300 {
compatible = "platform-uhci";
reg = <0xd8007300 0x200>;
interrupts = <0>;
};
fb: fb@d8050800 {
compatible = "wm,wm8505-fb";
reg = <0xd8050800 0x200>;
};
ge_rops@d8050400 {
compatible = "wm,prizm-ge-rops";
reg = <0xd8050400 0x100>;
};
uart0: serial@d8200000 {
compatible = "via,vt8500-uart";
reg = <0xd8200000 0x1040>;
interrupts = <32>;
clocks = <&clkuart0>;
status = "disabled";
};
uart1: serial@d82b0000 {
compatible = "via,vt8500-uart";
reg = <0xd82b0000 0x1040>;
interrupts = <33>;
clocks = <&clkuart1>;
status = "disabled";
};
uart2: serial@d8210000 {
compatible = "via,vt8500-uart";
reg = <0xd8210000 0x1040>;
interrupts = <47>;
clocks = <&clkuart2>;
status = "disabled";
};
uart3: serial@d82c0000 {
compatible = "via,vt8500-uart";
reg = <0xd82c0000 0x1040>;
interrupts = <50>;
clocks = <&clkuart3>;
status = "disabled";
};
uart4: serial@d8370000 {
compatible = "via,vt8500-uart";
reg = <0xd8370000 0x1040>;
interrupts = <31>;
clocks = <&clkuart4>;
status = "disabled";
};
uart5: serial@d8380000 {
compatible = "via,vt8500-uart";
reg = <0xd8380000 0x1040>;
interrupts = <30>;
clocks = <&clkuart5>;
status = "disabled";
};
rtc@d8100000 {
compatible = "via,vt8500-rtc";
reg = <0xd8100000 0x10000>;
interrupts = <48>;
};
sdhc@d800a000 {
compatible = "wm,wm8505-sdhc";
reg = <0xd800a000 0x400>;
interrupts = <20>, <21>;
clocks = <&clksdhc>;
bus-width = <4>;
};
};
};
|
