summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/mt6589.dtsi
blob: 70df00a7bb26701dc2cdeb21272e45c7298af5ea (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2014 MundoReader S.L.
 * Author: Matthias Brugger <matthias.bgg@gmail.com>
 *
*/

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "mediatek,mt6589";
	interrupt-parent = <&sysirq>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt6589-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};

	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		system_clk: dummy13m {
			compatible = "fixed-clock";
			clock-frequency = <13000000>;
			#clock-cells = <0>;
		};

		rtc_clk: dummy32k {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			#clock-cells = <0>;
		};

		uart_clk: dummy26m {
			compatible = "fixed-clock";
			clock-frequency = <26000000>;
			#clock-cells = <0>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		timer: timer@10008000 {
			compatible = "mediatek,mt6577-timer";
			reg = <0x10008000 0x80>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&system_clk>, <&rtc_clk>;
			clock-names = "system-clk", "rtc-clk";
		};

		sysirq: interrupt-controller@10200100 {
			compatible = "mediatek,mt6589-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0x10200100 0x1c>;
		};

		gic: interrupt-controller@10211000 {
			compatible = "arm,cortex-a7-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0x10211000 0x1000>,
			      <0x10212000 0x2000>,
			      <0x10214000 0x2000>,
			      <0x10216000 0x2000>;
		};

		uart0: serial@11006000 {
			compatible = "mediatek,mt6577-uart";
			reg = <0x11006000 0x400>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart1: serial@11007000 {
			compatible = "mediatek,mt6577-uart";
			reg = <0x11007000 0x400>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart2: serial@11008000 {
			compatible = "mediatek,mt6577-uart";
			reg = <0x11008000 0x400>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart3: serial@11009000 {
			compatible = "mediatek,mt6577-uart";
			reg = <0x11009000 0x400>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		wdt: watchdog@10000000 {
			compatible = "mediatek,mt6589-wdt";
			reg = <0x10000000 0x44>;
		};
	};
};