summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
blob: 84671950ca0d6a0c360cd78bd8c14c519f3d9287 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: GENI Serial Engine QUP Wrapper Controller

maintainers:
  - Mukesh Savaliya <msavaliy@codeaurora.org>
  - Akash Asthana <akashast@codeaurora.org>

description: |
 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
 is a programmable module for supporting a wide range of serial interfaces
 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
 Wrapper controller is modeled as a node with zero or more child nodes each
 representing a serial engine.

properties:
  compatible:
    enum:
      - qcom,geni-se-qup

  reg:
    description: QUP wrapper common register address and length.
    maxItems: 1

  clock-names:
    items:
      - const: m-ahb
      - const: s-ahb

  clocks:
    items:
      - description: Master AHB Clock
      - description: Slave AHB Clock

  "#address-cells":
    const: 2

  "#size-cells":
    const: 2

  ranges: true

  interconnects:
    maxItems: 1

  interconnect-names:
    const: qup-core

required:
  - compatible
  - reg
  - clock-names
  - clocks
  - "#address-cells"
  - "#size-cells"
  - ranges

patternProperties:
  "^.*@[0-9a-f]+$":
    type: object
    description: Common properties for GENI Serial Engine based I2C, SPI and
                 UART controller.

    properties:
      reg:
        description: GENI Serial Engine register address and length.
        maxItems: 1

      clock-names:
        const: se

      clocks:
        description: Serial engine core clock needed by the device.
        maxItems: 1

      interconnects:
        minItems: 2
        maxItems: 3

      interconnect-names:
        minItems: 2
        items:
          - const: qup-core
          - const: qup-config
          - const: qup-memory

    required:
      - reg
      - clock-names
      - clocks

  "spi@[0-9a-f]+$":
    type: object
    description: GENI serial engine based SPI controller. SPI in master mode
                 supports up to 50MHz, up to four chip selects, programmable
                 data path from 4 bits to 32 bits and numerous protocol
                 variants.
    $ref: /spi/spi-controller.yaml#

    properties:
      compatible:
        enum:
          - qcom,geni-spi

      interrupts:
        maxItems: 1

      "#address-cells":
        const: 1

      "#size-cells":
        const: 0

    required:
      - compatible
      - interrupts
      - "#address-cells"
      - "#size-cells"

  "i2c@[0-9a-f]+$":
    type: object
    description: GENI serial engine based I2C controller.
    $ref: /schemas/i2c/i2c-controller.yaml#

    properties:
      compatible:
        enum:
          - qcom,geni-i2c

      interrupts:
        maxItems: 1

      "#address-cells":
        const: 1

      "#size-cells":
        const: 0

      clock-frequency:
        description: Desired I2C bus clock frequency in Hz.
        default: 100000

    required:
      - compatible
      - interrupts
      - "#address-cells"
      - "#size-cells"

  "serial@[0-9a-f]+$":
    type: object
    description: GENI Serial Engine based UART Controller.
    $ref: /schemas/serial.yaml#

    properties:
      compatible:
        enum:
          - qcom,geni-uart
          - qcom,geni-debug-uart

      interrupts:
        minItems: 1
        maxItems: 2
        items:
          - description: UART core irq
          - description: Wakeup irq (RX GPIO)

    required:
      - compatible
      - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        geniqup@8c0000 {
            compatible = "qcom,geni-se-qup";
            reg = <0 0x008c0000 0 0x6000>;
            clock-names = "m-ahb", "s-ahb";
            clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
                <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
            #address-cells = <2>;
            #size-cells = <2>;
            ranges;

            i2c0: i2c@a94000 {
                compatible = "qcom,geni-i2c";
                reg = <0 0xa94000 0 0x4000>;
                interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
                clock-names = "se";
                clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
                pinctrl-names = "default", "sleep";
                pinctrl-0 = <&qup_1_i2c_5_active>;
                pinctrl-1 = <&qup_1_i2c_5_sleep>;
                #address-cells = <1>;
                #size-cells = <0>;
            };

            uart0: serial@a88000 {
                compatible = "qcom,geni-uart";
                reg = <0 0xa88000 0 0x7000>;
                interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
                clock-names = "se";
                clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
                pinctrl-names = "default", "sleep";
                pinctrl-0 = <&qup_1_uart_3_active>;
                pinctrl-1 = <&qup_1_uart_3_sleep>;
            };
        };
    };

...