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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon System Reset Controller
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: |
Please also refer to reset.txt in this directory for common reset
controller binding usage.
The reset controller registers are part of the system-ctl block on
hi3660 and hi3670 SoCs.
properties:
compatible:
oneOf:
- items:
- const: hisilicon,hi3660-reset
- items:
- const: hisilicon,hi3670-reset
- const: hisilicon,hi3660-reset
hisilicon,rst-syscon:
description: phandle of the reset's syscon.
$ref: /schemas/types.yaml#/definitions/phandle
'#reset-cells':
description: |
Specifies the number of cells needed to encode a reset source.
Cell #1 : offset of the reset assert control register from the syscon
register base
offset + 4: deassert control register
offset + 8: status control register
Cell #2 : bit position of the reset in the reset control register
const: 2
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3660-clock.h>
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3660-iomcu", "syscon";
reg = <0xffd7e000 0x1000>;
};
iomcu_rst: iomcu_rst_controller {
compatible = "hisilicon,hi3660-reset";
hisilicon,rst-syscon = <&iomcu>;
#reset-cells = <2>;
};
/* Specifying reset lines connected to IP modules */
i2c@ffd71000 {
compatible = "snps,designware-i2c";
reg = <0xffd71000 0x1000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
resets = <&iomcu_rst 0x20 3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
};
...
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