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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
allOf:
- $ref: "mmc-controller.yaml"
description: |
The Enhanced Secure Digital Host Controller on Freescale i.MX family
provides an interface for MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties described
by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
properties:
compatible:
enum:
- fsl,imx25-esdhc
- fsl,imx35-esdhc
- fsl,imx51-esdhc
- fsl,imx53-esdhc
- fsl,imx6q-usdhc
- fsl,imx6sl-usdhc
- fsl,imx6sx-usdhc
- fsl,imx6ull-usdhc
- fsl,imx7d-usdhc
- fsl,imx7ulp-usdhc
- fsl,imx8mq-usdhc
- fsl,imx8mm-usdhc
- fsl,imx8mn-usdhc
- fsl,imx8mp-usdhc
- fsl,imx8qm-usdhc
- fsl,imx8qxp-usdhc
reg:
maxItems: 1
interrupts:
maxItems: 1
fsl,wp-controller:
description: |
boolean, if present, indicate to use controller internal write protection.
type: boolean
fsl,delay-line:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify the number of delay cells for override mode.
This is used to set the clock delay for DLL(Delay Line) on override mode
to select a proper data sampling window in case the clock quality is not good
due to signal path is too long on the board. Please refer to eSDHC/uSDHC
chapter, DLL (Delay Line) section in RM for details.
default: 0
voltage-ranges:
$ref: '/schemas/types.yaml#/definitions/uint32-matrix'
description: |
Specify the voltage range in case there are software transparent level
shifters on the outputs of the controller. Two cells are required, first
cell specifies minimum slot voltage (mV), second cell specifies maximum
slot voltage (mV).
items:
items:
- description: value for minimum slot voltage
- description: value for maximum slot voltage
maxItems: 1
fsl,tuning-start-tap:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify the start delay cell point when send first CMD19 in tuning procedure.
default: 0
fsl,tuning-step:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify the increasing delay cell steps in tuning procedure.
The uSDHC use one delay cell as default increasing step to do tuning process.
This property allows user to change the tuning step to more than one delay
cells which is useful for some special boards or cards when the default
tuning step can't find the proper delay window within limited tuning retries.
default: 0
fsl,strobe-dll-delay-target:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify the strobe dll control slave delay target.
This delay target programming host controller loopback read clock, and this
property allows user to change the delay target for the strobe input read clock.
If not use this property, driver default set the delay target to value 7.
Only eMMC HS400 mode need to take care of this property.
default: 0
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
mmc@70004000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70004000 0x4000>;
interrupts = <1>;
fsl,wp-controller;
};
mmc@70008000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70008000 0x4000>;
interrupts = <2>;
cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
};
|
