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* Mediatek UART APDMA Controller
Required properties:
- compatible should contain:
* "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
* "mediatek,mt6577-uart-dma" for MT6577 and all of the above
- reg: The base address of the APDMA register bank.
- interrupts: A single interrupt specifier.
One interrupt per dma-requests, or 8 if no dma-requests property is present
- dma-requests: The number of DMA channels
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: The APDMA clock for register accesses
- mediatek,dma-33bits: Present if the DMA requires support
Examples:
apdma: dma-controller@11000400 {
compatible = "mediatek,mt2712-uart-dma";
reg = <0 0x11000400 0 0x80>,
<0 0x11000480 0 0x80>,
<0 0x11000500 0 0x80>,
<0 0x11000580 0 0x80>,
<0 0x11000600 0 0x80>,
<0 0x11000680 0 0x80>,
<0 0x11000700 0 0x80>,
<0 0x11000780 0 0x80>,
<0 0x11000800 0 0x80>,
<0 0x11000880 0 0x80>,
<0 0x11000900 0 0x80>,
<0 0x11000980 0 0x80>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
dma-requests = <12>;
clocks = <&pericfg CLK_PERI_AP_DMA>;
clock-names = "apdma";
mediatek,dma-33bits;
#dma-cells = <1>;
};
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