summaryrefslogtreecommitdiffstats
path: root/tools/testing/cxl
AgeCommit message (Expand)AuthorFilesLines
2022-02-08tools/testing/cxl: Add a physical_node linkDan Williams1-2/+19
2022-02-08tools/testing/cxl: Enumerate mock decodersDan Williams1-20/+98
2022-02-08tools/testing/cxl: Mock one level of switchesDan Williams1-41/+97
2022-02-08tools/testing/cxl: Fix root port to host bridge assignmentDan Williams1-1/+1
2022-02-08tools/testing/cxl: Mock dvsec_ranges()Dan Williams1-0/+10
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky2-0/+16
2022-02-08cxl/memdev: Add numa_node attributeDan Williams1-0/+1
2022-02-08cxl/pci: Emit device serial numberDan Williams1-0/+1
2022-02-08cxl/pci: Implement wait for media activeBen Widawsky1-0/+8
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams3-30/+21
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2-2/+5
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams4-0/+86
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams5-128/+71
2022-02-08cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams1-0/+4
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams2-26/+0
2022-02-08cxl/core/port: Rename bus.c to port.cDan Williams1-1/+1
2021-11-15cxl/test: Mock acpi_table_parse_cedt()Dan Williams4-48/+59
2021-11-15tools/testing/cxl: add mock output for the GET_HEALTH_INFO commandVishal Verma1-0/+49
2021-11-15cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny1-25/+25
2021-09-21tools/testing/cxl: Introduce a mock memory device + driverDan Williams5-1/+354
2021-09-21tools/testing/cxl: Introduce a mocked-up CXL port hierarchyDan Williams7-0/+871