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path: root/include/drm/i915_pciids.h
AgeCommit message (Expand)AuthorFilesLines
2020-11-06drm/i915: Sort EHL/JSL PCI IDsVille Syrjälä1-7/+7
2020-11-03drm/i915/ehl: Remove invalid PCI IDAnusha Srivatsa1-1/+0
2020-10-20drm/i915: Sort ICL PCI IDsVille Syrjälä1-8/+8
2020-10-20drm/i915: Sort CNL PCI IDsVille Syrjälä1-9/+9
2020-10-20drm/i915: Sort CFL PCI IDsVille Syrjälä1-2/+2
2020-10-20drm/i915: Sort CML PCI IDsVille Syrjälä1-6/+6
2020-10-20drm/i915: Sort KBL PCI IDsVille Syrjälä1-4/+4
2020-10-20drm/i915: Sort SKL PCI IDsVille Syrjälä1-4/+4
2020-10-20drm/i915: Sort HSW PCI IDsVille Syrjälä1-17/+17
2020-10-20drm/i915: Ocd the HSW PCI ID hex numbersVille Syrjälä1-3/+3
2020-10-20drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e commentsVille Syrjälä1-6/+6
2020-10-20drm/i915: Add SKL GT1.5 PCI IDsAlexei Podtelezhnikov1-3/+6
2020-10-20drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULTAlexei Podtelezhnikov1-3/+3
2020-10-20drm/i915: Reclassify SKL 0x192a as GT3Alexei Podtelezhnikov1-1/+1
2020-10-20drm/i915: Update Haswell PCI IDsAlexei Podtelezhnikov1-1/+1
2020-10-14drm/i915/jsl: Split EHL/JSL platform info and PCI idsTejas Upadhyay1-3/+6
2020-10-07drm/i915/dg1: add more PCI idsLucas De Marchi1-1/+4
2020-08-31drm/i915: break TGL pci-ids in GT 1 & 2Lionel Landwerlin1-4/+10
2020-08-17drm/i915: Remove dubious Valleyview PCI IDsAlexei Podtelezhnikov1-3/+1
2020-07-14drm/i915/dg1: Add DG1 PCI IDsAbdiel Janulgue1-0/+4
2020-07-07drm/i915/ehl: Add new PCI idsJosé Roberto de Souza1-0/+4
2020-05-19drm/i915/rkl: Add RKL platform info and PCI idsMatt Roper1-0/+9
2020-03-18drm/i915/tgl: Add new PCI IDs to TGLSwathi Dhanavanthri1-2/+6
2019-12-12drm/i915/cml: Separate U series pci id from origianl list.Lee Shawn C1-7/+13
2019-12-12drm/i915/cml: Remove unsupport PCI IDLee Shawn C1-4/+0
2019-12-06drm/i915: Add new EHL/JSL PCI idsJosé Roberto de Souza1-2/+5
2019-08-15drm/i915/cml: Add Missing PCI IDsAnusha Srivatsa1-1/+4
2019-07-11drm/i915/tgl: Add TGL PCI IDsLucas De Marchi1-0/+10
2019-06-26drm/i915/icl: Add missing device IDMika Kahola1-1/+2
2019-05-14drm/i915/icl: More workaround for port F detection due to broken VBTsImre Deak1-2/+2
2019-04-01drm/i915: Split some PCI ids into separate groupsTvrtko Ursulin1-49/+124
2019-04-01drm/i915: Split Pineview device info into desktop and mobileTvrtko Ursulin1-2/+4
2019-03-22drm/i915/ehl: Add EHL platform info and PCI IDsJames Ausmus1-0/+7
2019-03-19drm/i915/cml: Add CML PCI IDSAnusha Srivatsa1-1/+27
2019-03-12drm/i915: Add new ICL PCI IDJosé Roberto de Souza1-1/+2
2019-01-31drm/i915/cfl: Adding another PCI Device ID.Rodrigo Vivi1-0/+4
2019-01-23drm/i915/icl: Adding few more device IDs for Ice LakeRodrigo Vivi1-0/+4
2018-10-11drm/i915/aml: Add new Amber Lake PCI IDJosé Roberto de Souza1-3/+8
2018-10-05drm/i915: Redefine some Whiskey Lake SKUsRodrigo Vivi1-5/+5
2018-08-08drm/i915/cfl: Add a new CFL PCI ID.Rodrigo Vivi1-0/+1
2018-06-18drm/i915/aml: Introducing Amber Lake platformJosé Roberto de Souza1-2/+7
2018-06-18drm/i915/whl: Introducing Whiskey Lake platformJosé Roberto de Souza1-10/+18
2018-04-23drm/i915/kbl: Add KBL GT2 skuMatt Atwood1-0/+1
2018-02-22drm/i915/icl: Add the ICL PCI IDsPaulo Zanoni1-0/+12
2018-02-14drm/i915/cnl: Sync PCI ID with Spec.Rodrigo Vivi1-7/+8
2018-01-30drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.Rodrigo Vivi1-11/+7
2017-12-20drm/i915/cfl: Adding more Coffee Lake PCI IDs.Rodrigo Vivi1-6/+22
2017-12-15x86/gpu: add CFL to early quirksLucas De Marchi1-0/+6
2017-09-21drm/i915/kbl: Change a KBL pci id to GT2 from GT1.5Anuj Phogat1-1/+1
2017-09-01drm/i915: add GT number to intel_device_infoLionel Landwerlin1-57/+95
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-18 12:37:00 +0000