| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-01-26 | Merge branches 'clk-iproc', 'clk-mvebu' and 'clk-qcom-a53' into clk-next | Stephen Boyd | 10 | -102/+737 |
| 2018-01-26 | Merge branches 'clk-at91', 'clk-imx7ulp', 'clk-axigen', 'clk-si5351' and 'clk... | Stephen Boyd | 7 | -41/+146 |
| 2018-01-26 | Merge branches 'clk-spreadtrum', 'clk-mvebu-dvfs', 'clk-qoriq', 'clk-imx' and... | Stephen Boyd | 29 | -81/+7213 |
| 2018-01-26 | Merge branches 'clk-qcom-alpha-pll', 'clk-check-ops-ptr', 'clk-protect-rate' ... | Stephen Boyd | 15 | -5241/+918 |
| 2018-01-02 | clk: qcom: Add APCS clock controller support | Georgi Djakov | 3 | -0/+150 |
| 2018-01-02 | clk: qcom: Add regmap mux-div clocks support | Georgi Djakov | 3 | -0/+276 |
| 2018-01-02 | clk: qcom: Add A53 PLL support | Georgi Djakov | 3 | -0/+118 |
| 2017-12-28 | clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO() | Gomonovych, Vasyl | 1 | -4/+1 |
| 2017-12-28 | clk: iproc: Minor tidy up of iproc pll data structures | Lori Hikichi | 1 | -47/+36 |
| 2017-12-28 | clk: iproc: Allow plls to do minor rate changes without reset | Lori Hikichi | 1 | -0/+47 |
| 2017-12-28 | clk: iproc: Fix error in the pll post divider rate calculation | Lori Hikichi | 1 | -16/+17 |
| 2017-12-28 | clk: iproc: Allow iproc pll to runtime calculate vco parameters | Lori Hikichi | 3 | -35/+92 |
| 2017-12-28 | clk: si5351: _si5351_clkout_reset_pll() can be static | Wu Fengguang | 1 | -1/+1 |
| 2017-12-28 | clk: pxa: unbreak lookup of CLK_POUT | Igor Grinberg | 1 | -1/+5 |
| 2017-12-21 | clk: si5351: Do not enable parent clocks on probe | Sergej Sawazki | 1 | -26/+9 |
| 2017-12-21 | clk: si5351: Rename internal plls to avoid name collisions | Sergej Sawazki | 1 | -1/+1 |
| 2017-12-21 | clk: si5351: Apply PLL soft reset before enabling the outputs | Sergej Sawazki | 1 | -0/+29 |
| 2017-12-21 | clk: si5351: Add DT property to enable PLL reset | Sergej Sawazki | 1 | -0/+3 |
| 2017-12-21 | clk: si5351: implement remove handler | Alexey Khoroshilov | 1 | -0/+13 |
| 2017-12-21 | clk: axi-clkgen: Round closest in round_rate() and recalc_rate() | Lars-Peter Clausen | 1 | -3/+7 |
| 2017-12-21 | clk: axi-clkgen: Correctly handle nocount bit in recalc_rate() | Lars-Peter Clausen | 1 | -5/+24 |
| 2017-12-21 | clk: Don't touch hardware when reparenting during registration | Stephen Boyd | 1 | -2/+5 |
| 2017-12-21 | clk: at91: pmc: Support backup for programmable clocks | Romain Izard | 3 | -0/+39 |
| 2017-12-21 | clk: at91: pmc: Save SCSR during suspend | Romain Izard | 1 | -2/+2 |
| 2017-12-21 | clk: at91: pmc: Wait for clocks when resuming | Romain Izard | 1 | -8/+16 |
| 2017-12-21 | clk: qcom: ipq8074: add misc resets for PCIE and NSS | Abhishek Sahu | 1 | -0/+42 |
| 2017-12-21 | clk: qcom: ipq8074: add GP and Crypto clocks | Abhishek Sahu | 1 | -0/+199 |
| 2017-12-21 | clk: qcom: ipq8074: add NSS ethernet port clocks | Abhishek Sahu | 1 | -0/+1288 |
| 2017-12-21 | clk: qcom: ipq8074: add NSS clocks | Abhishek Sahu | 1 | -0/+1034 |
| 2017-12-21 | clk: qcom: ipq8074: add PCIE, USB and SDCC clocks | Abhishek Sahu | 1 | -0/+994 |
| 2017-12-21 | clk: qcom: ipq8074: add remaining PLL’s | Abhishek Sahu | 1 | -1/+191 |
| 2017-12-21 | clk: qcom: ipq8074: fix missing GPLL0 divider width | Abhishek Sahu | 1 | -0/+1 |
| 2017-12-21 | clk: qcom: add parent map for regmap mux | Abhishek Sahu | 4 | -11/+18 |
| 2017-12-21 | clk: qcom: add read-only divider operations | Abhishek Sahu | 2 | -0/+30 |
| 2017-12-21 | clk: imx51: uart4, uart5 gates only exist on imx50, imx53 | Philipp Zabel | 1 | -4/+8 |
| 2017-12-21 | clk: qoriq: add more divider clocks support | Yuantian Tang | 1 | -1/+8 |
| 2017-12-21 | clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks | Gregory CLEMENT | 1 | -4/+217 |
| 2017-12-21 | clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFS | Gregory CLEMENT | 1 | -9/+73 |
| 2017-12-21 | clk: mvebu: armada-37xx-periph: cosmetic changes | Gregory CLEMENT | 1 | -8/+9 |
| 2017-12-21 | clk: sprd: add clocks support for SC9860 | Chunyan Zhang | 3 | -0/+1987 |
| 2017-12-21 | clk: sprd: add adjustable pll support | Chunyan Zhang | 3 | -0/+375 |
| 2017-12-21 | clk: sprd: add composite clock support | Chunyan Zhang | 3 | -0/+112 |
| 2017-12-21 | clk: sprd: add divider clock support | Chunyan Zhang | 3 | -0/+166 |
| 2017-12-21 | clk: sprd: add mux clock support | Chunyan Zhang | 3 | -0/+151 |
| 2017-12-21 | clk: sprd: add gate clock support | Chunyan Zhang | 3 | -0/+171 |
| 2017-12-21 | clk: sprd: Add common infrastructure | Chunyan Zhang | 6 | -0/+143 |
| 2017-12-21 | clk: move clock common macros out from vendor directories | Chunyan Zhang | 2 | -47/+0 |
| 2017-12-19 | clk: fix set_rate_range when current rate is out of range | Jerome Brunet | 1 | -4/+33 |
| 2017-12-19 | clk: add clk_rate_exclusive api | Jerome Brunet | 1 | -0/+172 |
| 2017-12-19 | clk: cosmetic changes to clk_summary debugfs entry | Jerome Brunet | 1 | -3/+4 |
