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path: root/drivers/staging/mt7621-pci
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2021-08-26staging: mt7621-pci: fix hang when nothing is connected to pcie portsSergio Paracuellos1-2/+11
When nothing is connected to pcie ports, each port is set to reset state. When this occurs, next access result in a hang on boot as follows: mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK) mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK) mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK) [ HANGS HERE ] Fix this just detecting 'nothing is connected state' to avoid next accesses to pcie port related configuration registers. Fixes: b99cc3a2b6b6 ("staging: mt7621-pci: avoid custom 'map_irq' function") Cc: stable <stable@vger.kernel.org> Reported-by: DENG Qingfang <dqfext@gmail.com> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210823170803.2108-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-07-27staging: mt7621-pci: avoid to re-disable clock for those pcies not in useSergio Paracuellos1-1/+0
Clock driver for this SoC is using some gates to properly enabling and disabling the access to peripherals. Those gates that are not in use are properly being automatically disabled by the kernel. Pcie driver is explicitly doing a 'clk_disable_unprepare' call for gates of those pcies that are not used. Since kernel has already disabled them, the following warnings appear: WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:952 clk_core_disable+0xe4/0x100 pcie2 already disabled Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.14.0 #0 Stack : 81661680 80082d00 807c0000 00000004 00000000 80a20000 80860000 80792380 814503d4 80862e83 00000000 1431b70 81454360 00000000 00000000 80792380 81431a08 ffffefff fffffea 00000000 81431a14 0000007b 80868820 ffffffff 80792380 1431c70 803d7a24 00000009 807f3a74 00000001 815df810 00000018 0000000 80a20000 ... Call Trace: [<80007ed8>] show_stack+0x28/0xf0 [<80381e40>] dump_stack_lvl+0x60/0x80 [<8002cf90>] __warn+0xcc/0x140 [<8002d090>] warn_slowpath_fmt+0x8c/0xac [<803d7a24>] clk_core_disable+0xe4/0x100 [<803da468>] clk_disable+0x38/0x58 [<804cb730>] mt7621_pci_probe+0x980/0xa50 [<8041e624>] platform_probe+0x50/0xbc [<8041bfe4>] really_probe.part.0+0xa8/0x340 [<8041c3dc>] driver_probe_device+0x4c/0x154 [<8041cb88>] __driver_attach+0xb4/0x1b4 [<80419a38>] bus_for_each_dev+0x68/0xa4 [<8041b1e8>] bus_add_driver+0x134/0x214 [<8041d3bc>] driver_register+0x98/0x154 [<80001648>] do_one_initcall+0x50/0x1a8 [<808ea1fc>] kernel_init_freeable+0x270/0x30c [<806dd9dc>] kernel_init+0x20/0x110 [<80002d98>] ret_from_kernel_thread+0x14/0x1c WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:810 clk_core_unprepare+0xf4/0x194 pcie2 already unprepared Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 5.14.0 #0 Stack : 81661680 80082d00 807c0000 00000004 00000000 00000000 81431bc4 80a20000 80860000 80792380 814503d4 80862e83 00000000 00000001 81431b70 81454360 00000000 00000000 80792380 81431a08 ffffefff 00000000 ffffffea 00000000 81431a14 0000009b 80868820 ffffffff 80792380 00000001 81431c70 803d7764 00000009 807f3a74 00000001 815df810 00000018 8040b36c 00000000 80a20000 ... Call Trace: [<80007ed8>] show_stack+0x28/0xf0 [<80381e40>] dump_stack_lvl+0x60/0x80 [<8002cf90>] __warn+0xcc/0x140 [<8002d090>] warn_slowpath_fmt+0x8c/0xac [<803d7764>] clk_core_unprepare+0xf4/0x194 [<803d97c4>] clk_unprepare+0x30/0x48 [<804cb738>] mt7621_pci_probe+0x988/0xa50 [<8041e624>] platform_probe+0x50/0xbc [<8041bfe4>] really_probe.part.0+0xa8/0x340 [<8041c3dc>] driver_probe_device+0x4c/0x154 [<8041cb88>] __driver_attach+0xb4/0x1b4 [<80419a38>] bus_for_each_dev+0x68/0xa4 [<8041b1e8>] bus_add_driver+0x134/0x214 [<8041d3bc>] driver_register+0x98/0x154 [<80001648>] do_one_initcall+0x50/0x1a8 [<808ea1fc>] kernel_init_freeable+0x270/0x30c [<806dd9dc>] kernel_init+0x20/0x110 [<80002d98>] ret_from_kernel_thread+0x14/0x1c Avoid to explicitly disable already disabled pcie gates fixes the problem. Fixes: cc4e864a5ce4 ("staging: mt7621-pci: make use of kernel clock apis") Reported-by: DENG Qingfang <dqfext@gmail.com> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210727054058.10612-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-15staging: mt7621-pci: remove 'mt7621_pci_parse_request_of_pci_ranges'Sergio Paracuellos1-73/+27
After 'PCI_IOBASE' is defined for ralink, ranges are properly parsed using pci generic APIS and there is no need to parse anything manually. So function 'mt7621_pci_parse_request_of_pci_ranges' used for this can be enterely removed. Since we have to configure iocu memory regions and pci io windows resources must be retrieved accordly from 'bridge->windows' but there is no need to store anything as driver private data. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210614100617.28753-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-09staging: mt7621-pci: make use of 'pcie_port_write'Sergio Paracuellos1-8/+4
Function 'mt7621_pcie_enable_port' is calculating an offset to write some port related registers. Instead of doing that just make use of already existent 'pcie_write_port' function and use virtualy mapped base address with registers. This increase readability and allow us to remove also two defitions not used else where. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210607120153.24989-7-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-09staging: mt7621-pci: parse some dt properties from root port child nodesSergio Paracuellos1-11/+38
Properties 'clocks', 'resets' and 'phys' have been moved from parent node to the root port children. Hence we have to adapt the way device tree is parsed in driver code to properly align things and make all the stuff work. Note that we moved from using 'devm_reset_control_get_exclusive() to 'of_reset_control_get_exclusive()' so we need to properly call the 'reset_control_put()' function manually in error and remove paths. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210607120153.24989-6-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-09staging: mt7621-pci: use {readl|writel}_relaxed instead of readl/writelSergio Paracuellos1-7/+7
The driver does not perform DMA, so it's safe to use the relaxed version for both readl and writel operations. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210607120153.24989-4-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-09staging: mt7621-pci: remove 'RALINK_PCI_BAR0SETUP_ADDR' definitionSergio Paracuellos1-2/+1
Instead of define RALINK_PCI_BAR0SETUP_ADDR just use standard pci defnition for this which is 'PCI_BASE_ADDRESS_0'. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210607120153.24989-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-06-09staging: mt7621-pci: make cleaner 'mt7621_pcie_enable_ports'Sergio Paracuellos1-16/+8
Function 'mt7621_pcie_enable_ports' call 'mt7621_pcie_enable_port' for each available pcie port. Instead of having two for loops there just move needed initialization. There is one setting that can be removed which is the set for 'PCI_COMMAND_MASTER' bit. Pci drivers are in charge of set that bit if is really needed and should be not a mission of the controller to do that. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210607120153.24989-2-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-10staging: mt7621-pci: remove two blank linesSergio Paracuellos1-2/+0
There are useless two blank lines in code that can be removed. Hence, remove them. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210505121736.6459-9-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-10staging: mt7621-pci: avoid custom 'map_irq' functionSergio Paracuellos1-88/+0
Custom function for 'map_irq' was introduced in commit fab6710e4c51 ("staging: mt7621-pci: fix PCIe interrupt mapping") After some testing in an adquired device with a similar pci layout that those that was having problems, I got into a better way to solve the issue just using device tree 'interrupt-map' and 'interrupt-map-mask' properties. For this to be possible we must avoid custom configuration of the virtual bridges registers from driver code. Doing in this way buses are not reconfigured so we can properly use bus related bits and mask in device tree to map correctly the interrupts. Hence remove custom configuration of the bridges as well as custom 'map_irq' related stuff. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210505121736.6459-8-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-10staging: mt7621-pci: directly return 'mt7621_pcie_register_host'Sergio Paracuellos1-7/+1
Return code after call function 'mt7621_pcie_register_host' is being checked to give an error message. This function internally is calling 'pci_host_probe' which if something fails will complain already. Hence, directly return result of this call making decrease a bit LOC. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210505121736.6459-7-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-10staging: mt7621-pci: replace mdelay with msleepSergio Paracuellos1-2/+2
There are two mdelay calls in driver code located in 'mt7621_pcie_reset_assert' and 'mt7621_pcie_reset_rc_deassert' functions. Both of them are not called in an interrupt handler nor holding any spinlock. Hence, the function mdelay in them can be replaced with msleep, to reduce busy wait. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210505121736.6459-6-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-10staging: mt7621-pci: group io resource assignments all togetherSergio Paracuellos1-2/+2
To improve a bit readabily group all the IO resource related assignments together. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210505121736.6459-5-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-10staging: mt7621-pci: remove some not needed includesSergio Paracuellos1-5/+0
Some includes used here are not really necessary for the code to compile properly. Hence remove them. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210505121736.6459-4-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-10staging: mt7621-pci: avoid to set gpio mode in driverSergio Paracuellos1-7/+0
Gpio mode for the pcie pins must be request from device tree using pinctrl driver. Pinctrl driver is already setting this pcie pins as GPIO if it is requested. Hence, remove it from here. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210505121736.6459-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-05-10staging: mt7621-pci: make use of kernel clock apisSergio Paracuellos1-18/+26
MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' Hence, we can make use of kernel clock apis and avoid to directly set bits in clock gate related registers for pci. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210505121736.6459-2-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-04-11staging: mt7621-pci: stop using of_pci_range_to_resourceIlya Lipnitskiy1-5/+6
The logic here was already overriding the erroneous IO addresses returned from of_pci_range_to_resource, which is the bulk of the logic. So stop using it altogether and initialize the fields explicitly, as done in aeba3731b150 ("powerpc/pci: Fix IO space breakage after of_pci_range_to_resource() change"). Cc: Sergio Paracuellos <sergio.paracuellos@gmail.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Link: https://lore.kernel.org/r/20210410173331.57949-1-ilya.lipnitskiy@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-03-10Staging: mt7621-pci: fixed a blank line coding style issueSelvakumar Elangovan1-1/+0
Removed an unnecessary blank line before closing brace reported by checkpatch.pl Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Selvakumar Elangovan <selvakumar16197@gmail.com> Link: https://lore.kernel.org/r/20210217070710.7359-1-selvakumar16197@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-26staging: mt7621-pci: remove 'RALINK_PCI_IMBASEBAR0_ADDR' registerSergio Paracuellos1-4/+0
Register 'RALINK_PCI_IMBASEBAR0_ADDR' contains internal memory base address for BAR0. We don't really need to write anything there at all since its initial value contains always a desired valid value. Hence remove register definition and related code. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201123093637.8300-8-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-26staging: mt7621-pci: convert to use 'devm_platform_ioremap_resource'Sergio Paracuellos1-20/+4
Instead of getting resources parsing from DT first and remaping afterwards, this can be done in one step using the kernel function 'devm_platform_ioremap_resource'. Hence, update to use it. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201123093637.8300-7-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-26staging: mt7621-pci: parse and prepare resources in ↵Sergio Paracuellos1-23/+21
'mt7621_pci_parse_request_of_pci_ranges' Remove 'mt7621_pcie_add_resources' where resources are added to the host windows moving this code into the function where all the parsing and preparing code is being done: 'mt7621_pci_parse_request_of_pci_ranges'. The memory resource has been properly parsed for the PCI APIs so we only need to retrieve it and use it in those places we need. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201123093637.8300-6-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-26staging: mt7621-pci: review 'pci_host_bridge' assigned variablesSergio Paracuellos1-2/+0
PCI kernel apis now set some variables related with pci_host_bridge by default and it is not necessary to setup them in driver code. Host bridge parent device is set by default to the platform device and 'swizzle_irq' is also set to its default function. These two are not necessary to be set here. Hence remove them. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201123093637.8300-5-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-26staging: mt7621-pci: add comment to clarify IO resource in this driverSergio Paracuellos1-0/+7
Because IO_SPACE_LIMIT for mips is 0xFFFF but this platform uses PĈI IO resource at 0x001e160000. Hence instead of directly use some more accurate functions from the PCI kernel for this driver some things must be done in a different way to make things work. Add this explanation as a comment where the IO resource is parsed and virtually mapped into memory. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201123093637.8300-4-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-26staging: mt7621-pci: remove 'offset' with mem and io resource sizesSergio Paracuellos1-9/+2
Offset contains resources size for both io and memory resources. Those fields are directly initialized to zero and set up using 'pci_add_resource_offset' function. Instead of doing that remove them and use directly function 'pci_add_resource' where zero is passed directly to its internal call to 'pci_add_resource_offset'. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201123093637.8300-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-26staging: mt7621-pci: remove bus ranges related codeSergio Paracuellos1-13/+0
Bus ranges are now discovered by default. Hence remove its related code from the driver. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201123093637.8300-2-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-23Merge 5.10-rc5 into staging-testingGreg Kroah-Hartman1-12/+3
We want the staging/IIO fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-06staging: mt7621-pci: avoid to request pci bus resourcesSergio Paracuellos1-12/+3
After upgrading kernel to version 5.9.x the driver was not working anymore showing the following kernel trace: ... mt7621-pci 1e140000.pcie: resource collision: [mem 0x60000000-0x6fffffff] conflicts with pcie@1e140000 [mem 0x60000000-0x6fffffff] ------------[ cut here ]------------ WARNING: CPU: 2 PID: 73 at kernel/resource.c:1400 devm_request_resource+0xfc/0x10c Modules linked in: CPU: 2 PID: 73 Comm: kworker/2:1 Not tainted 5.9.2 #0 Workqueue: events deferred_probe_work_func Stack : 00000000 81590000 807d0a1c 808a0000 8fd49080 807d0000 00000009 808ac820 00000001 808338d0 7fff0001 800839dc 00000049 00000001 8fe51b00 367204ab 00000000 00000000 807d0a1c 807c0000 00000001 80082358 8fe50000 00559000 00000000 8fe519f1 ffffffff 00000005 00000000 00000001 00000000 807d0000 00000009 808ac820 00000001 808338d0 00000001 803bf1b0 00000008 81390008 Call Trace: [<8000d018>] show_stack+0x30/0x100 [<8032e66c>] dump_stack+0xa4/0xd4 [<8002db1c>] __warn+0xc0/0x134 [<8002dbec>] warn_slowpath_fmt+0x5c/0xac [<80033b34>] devm_request_resource+0xfc/0x10c [<80365ff8>] devm_request_pci_bus_resources+0x58/0xdc [<8048e13c>] mt7621_pci_probe+0x8dc/0xe48 [<803d2140>] platform_drv_probe+0x40/0x94 [<803cfd94>] really_probe+0x108/0x4ec [<803cd958>] bus_for_each_drv+0x70/0xb0 [<803d0388>] __device_attach+0xec/0x164 [<803cec8c>] bus_probe_device+0xa4/0xc0 [<803cf1c4>] deferred_probe_work_func+0x80/0xc4 [<80048444>] process_one_work+0x260/0x510 [<80048a4c>] worker_thread+0x358/0x5cc [<8004f7d0>] kthread+0x134/0x13c [<80007478>] ret_from_kernel_thread+0x14/0x1c ---[ end trace a9dd2e37537510d3 ]--- mt7621-pci 1e140000.pcie: Error requesting resources mt7621-pci: probe of 1e140000.pcie failed with error -16 ... With commit 669cbc708122 ("PCI: Move DT resource setup into devm_pci_alloc_host_bridge()"), the DT 'ranges' is parsed and populated into resources when the host bridge is allocated. The resources are requested as well, but that happens a 2nd time for this driver in mt7621_pcie_request_resources(). Hence we should avoid this second request. Also, the bus ranges was also populated by default, so we can remove it from mt7621_pcie_request_resources() to avoid the following trace if we don't avoid it: pci_bus 0000:00: busn_res: can not insert [bus 00-ff] under domain [bus 00-ff] (conflicts with (null) [bus 00-ff]) Function 'mt7621_pcie_request_resources' has been renamed into 'mt7621_pcie_add_resources' which now is a more accurate name for this function. Cc: stable@vger.kernel.org #5.9.x- Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20201102202515.19073-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-11-06Staging: mt7621-pci: Fix alignment warningsSiddhant Gupta1-2/+2
Fix the alignment issue pointed out by checkpatch Signed-off-by: Siddhant Gupta <siddhantgupta416@gmail.com> Link: https://lore.kernel.org/r/20201106093021.GA25237@Sleakybeast Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-09-13staging: mt7621-pci: Update driver TODO fileAbheek Dhawan1-1/+1
Removed extra whitespace Signed-off-by: Abheek Dhawan <adawesomeguy222@gmail.com> Link: https://lore.kernel.org/r/20200912064542.412487-1-adawesomeguy222@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-16staging: mt7621-pci: initialize 'n' variable when it is declaredSergio Paracuellos1-2/+1
Variable 'n' in 'mt7621_pcie_init_virtual_bridges' function can be directly initialized when it is declared instead of doing it before using it first. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200413155018.31921-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-16staging: mt7621-pci: add clarification comment in ↵Sergio Paracuellos1-0/+5
'mt7621_pcie_init_virtual_bridges' Add a comment explaining a bit what is going on in this function. It would be helfulp for other people for a better understanding of the code. Suggested-by: NeilBrown <neil@brown.name> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200413155018.31921-2-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-16staging: mt7621-pci: rename 'PCIE_P2P_MAX' into 'PCIE_P2P_CNT'Sergio Paracuellos1-8/+8
Definition 'PCIE_P2P_MAX' is '3'. The value here is not a MAXimum. It is a count or a number. It is how many masks there are. The masks are numbered 0, 1, 2 so the maximum is 2. Hence rename variable into 'PCIE_P2P_CNT' which is a more accurate name. Suggested-by: NeilBrown <neil@brown.name> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200413155018.31921-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-13staging: mt7621-pci: fix PCIe interrupt mappingSergio Paracuellos1-2/+34
MT7621 has three assigned interrupts for the pcie. This interrupts should properly being mapped taking into account which devices are finally connected in which bus according to link status. So the irq mappings should be as follows according to link status (three bits indicating which devices are link up): * For PCIe Bus 1 slot 0: - status = 0x2 || status = 0x6 => IRQ = pcie1_irq (24). - status = 0x4 => IRQ = pcie2_irq (25). - default => IRQ = pcie0_irq (23). * For PCIe Bus 2 slot 0: - status = 0x5 || status = 0x6 => IRQ = pcie2_irq (25). - default => IRQ = pcie1_irq (24). * For PCIe Bus 2 slot 1: - status = 0x5 || status = 0x6 => IRQ = pcie2_irq (25). - default => IRQ = pcie1_irq (24). * For PCIe Bus 3 any slot: - default => IRQ = pcie2_irq (25). Because of this, the function 'of_irq_parse_and_map_pci' cannot be used and we need to change device tree information from using the 'interrupt-map' and 'interrupt-map-mask' properties into an 'interrupts' property to be able to get irq information from the ports using the 'platform_get_irq' and storing an 'irq-map' into the pcie driver data node to properly map correct irq using a new 'mt7621_map_irq' function where this map will be read and the correct irq returned. Fixes: 46d093124df4 ("staging: mt7621-pci: improve interrupt mapping") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200413055942.2714-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-13staging: mt7621-pci: properly power off dual-ported pcie phySergio Paracuellos1-2/+10
Pcie phy for pcie0 and pcie1 is shared using a dual ported one. Current code was assuming that if nothing is connected in pcie0 it won't be also nothing connected in pcie1. This assumtion is wrong for some devices such us 'Mikrotik rbm33g' and 'ZyXEL LTE3301-PLUS' where only connecting a card to the second bus on the phy is possible. For such devices kernel hangs in the same point because of the wrong poweroff of the phy getting the following trace: mt7621-pci-phy 1e149000.pcie-phy: PHY for 0xbe149000 (dual port = 1) mt7621-pci-phy 1e14a000.pcie-phy: PHY for 0xbe14a000 (dual port = 0) mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK) [hangs] The wrong assumption is located in the 'mt7621_pcie_init_ports' function where we are just making a power off of the phy for slots 0 and 2 if nothing is connected in them. Hence, only poweroff the phy if nothing is connected in both slot 0 and slot 1 avoiding the kernel to hang. Fixes: 5737cfe87a9c ("staging: mt7621-pci: avoid to poweroff the phy for slot one") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200409111652.30964-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-23staging: mt7621-pci: avoid to set 'iomem_resource' addressesSergio Paracuellos1-2/+0
Setting up kernel resource 'iomem_resource' for PCI with addresses parsed from device tree gots into a conflict within the usb xhci driver: xhci-mtk 1e1c0000.xhci: can't request region for resource [mem 0x1e1c0000-0x1e1c0fff] xhci-mtk: probe of 1e1c0000.xhci failed with error -16 Don't assign it and maintain the default addresses for this resource seems to fix the problem. Checking legacy driver it is being only setting the 'ioport_resource'. Fixes: 09dd629eeabb ("staging: mt7621-pci: fix io space and properly set resource limits") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200322072128.4454-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-23staging: mt7621-pci: use builtin_platform_driver()Sergio Paracuellos1-6/+1
Macro builtin_platform_driver can be used for builtin drivers that don't do anything in driver init. So, use the macro builtin_platform_driver and remove some boilerplate code. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200321133624.31388-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-21staging: mt7621-pci: delete release gpios related codeSergio Paracuellos1-20/+7
Making gpio8 and gpio9 vendor specific and putting them into the specific dts file makes not needed to release gpios anymore because we are not occupying those pins in the first place if it is not necessary. When the device tree is parsed we can also check and return for the error because we rely in the fact that the related device for the board is correct. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200321072650.7784-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-21staging: mt7621-pci: avoid to poweroff the phy for slot oneSergio Paracuellos1-1/+2
Phy for slot 0 and 1 is shared and handled properly in slot 0. If there is only one port in use,(slot 0) we shall not call the 'phy_power_off' function with an invalid slot because kernel will crash with an unaligned access fault like the following: mt7621-pci 1e140000.pcie: Error applying setting, reverse things back mt7621-pci-phy 1e149000.pcie-phy: PHY for 0xbe149000 (dual port = 1) mt7621-pci-phy 1e14a000.pcie-phy: PHY for 0xbe14a000 (dual port = 0) mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK) Unhandled kernel unaligned access[#1]: CPU: 3 PID: 111 Comm: kworker/3:2 Not tainted 5.6.0-rc3-00347-g825c6f470c62-dirty #9 Workqueue: events deferred_probe_work_func $ 0 : 00000000 00000001 5f60d043 8fe1ba80 $ 4 : 0000010d 01eb9000 00000000 00000000 $ 8 : 294b4c00 80940000 00000008 000000ce $12 : 2e303030 00000000 00000000 65696370 $16 : ffffffed 0000010d 8e373cd0 8214c1e0 $20 : 00000000 82144c80 82144680 8214c250 $24 : 00000018 803ef8f4 $28 : 8e372000 8e373c60 8214c080 803940e8 Hi : 00000125 Lo : 122f2000 epc : 807b3328 mutex_lock+0x8/0x44 ra : 803940e8 phy_power_off+0x28/0xb0 Status: 1100fc03 KERNEL EXL IE Cause : 00800010 (ExcCode 04) BadVA : 0000010d PrId : 0001992f (MIPS 1004Kc) Modules linked in: Process kworker/3:2 (pid: 111, threadinfo=(ptrval), task=(ptrval), tls=00000000) Stack : 8e373cd0 803fe4f4 8e372000 8e373c90 8214c080 804fde1c 8e373c98 808d62f4 8e373c78 00000000 8214c254 804fe648 1e160000 804f27b8 00000001 808d62f4 00000000 00000001 8214c228 808d62f4 80930000 809a0000 8fd47e10 808d63d4 808d62d4 8fd47e10 808d0000 808d0000 8e373cd0 8e373cd0 809e2a74 809db510 809db510 00000006 00000001 00000000 00000000 00000000 01000000 1e1440ff ... Call Trace: [<807b3328>] mutex_lock+0x8/0x44 [<803940e8>] phy_power_off+0x28/0xb0 [<804fe648>] mt7621_pci_probe+0xc20/0xd18 [<80402ab8>] platform_drv_probe+0x40/0x94 [<80400a74>] really_probe+0x104/0x364 [<803feb74>] bus_for_each_drv+0x84/0xdc [<80400924>] __device_attach+0xdc/0x120 [<803ffb5c>] bus_probe_device+0xa0/0xbc [<80400124>] deferred_probe_work_func+0x7c/0xbc [<800420e8>] process_one_work+0x230/0x450 [<80042638>] worker_thread+0x330/0x5fc [<80048eb0>] kthread+0x12c/0x134 [<80007438>] ret_from_kernel_thread+0x14/0x1c Code: 24050002 27bdfff8 8f830000 <c0850000> 14a00005 00000000 00600825 e0810000 1020fffa Fixes: bf516f413f4e ("staging: mt7621-pci: use only two phys from device tree") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200320153837.20415-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: mt7621-pci: be sure gpio descriptor is null on failsSergio Paracuellos1-1/+3
Function 'devm_gpiod_get_index_optional' returns NULL if the descriptor is invalid and the error associated for the error pointer is ENOENT. Sometimes if the pin is just assigned the error associated for the pointer might not be ENOENT but other. In order to avoid weirds behaviours if this happen set descriptor to NULL in the driver port structure. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200320110123.9907-6-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: mt7621-pci: change variable to print for slotSergio Paracuellos1-1/+1
We are using the counter to print the slot which has been enabled. Use the correct associated slot for the port instead. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200320110123.9907-5-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-20staging: mt7621-pci: use only two phys from device treeSergio Paracuellos1-1/+6
In order to align work with the mt7621-pci-phy part of the driver and device tree which is now using only two real phys one of them dual ported properly parse the device tree and don't call phy initialization for the slot 1 because is being taking into account when the phy for the slot 0 is instantiated. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200320110123.9907-4-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-19staging: mt7621-pci: don't return if get gpio failsSergio Paracuellos1-4/+2
In some platforms gpio's are not used for reset but for other purposes. Because of that when we try to get them are valid gpio's but are already assigned to do other function. To avoid those kind of problems in those platforms just notice the fail in the kernel but continue doing normal boot. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200319161416.19033-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-19staging: mt7621-pci: fix register to set up virtual bridgesSergio Paracuellos1-1/+1
Instead of being using PCI Configuration and Status Register to set up virtual bridges we are using CONFIG_ADDR Register which is wrong. Hence, set the correct value. Fixes: 9a5e71a68d20 ("staging: mt7621-pci: simplify 'mt7621_pcie_init_virtual_bridges' function") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200319095733.1557-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-18staging: mt7621-pci: fix io space and properly set resource limitsSergio Paracuellos1-18/+25
Function 'mt7621_pci_parse_request_of_pci_ranges' is using 'of_pci_range_to_resource' to get both mem and io resources. Internally this function calls to 'pci_address_to_pio' which returns -1 if io space address is an address > IO_SPACE_LIMIT which is 0xFFFF for mips. This mt7621 soc has io space in physical address 0x1e160000. In order to fix this, overwrite invalid io 0xffffffff with properly values from the device tree and set mapped address of this resource as io port base memory address calling 'set_io_port_base' function. There is also need to properly setup resource limits and io and memory windows with properly parsed values instead of set them as 'no limit' which it is wrong. For any reason I don't really know legacy driver sets up mem window as 0xFFFFFFFF and any other value seems to does not work as expected, so set up also here with same values. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200318094445.19669-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-17staging: mt7621-pci: delete no more needed 'mt7621_reset_port'Sergio Paracuellos1-13/+0
After review all the resets at the beggining the function 'mt7621_reset_port' is not needed anymore. Hence delete it and its uses. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200313200913.24321-7-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-17staging: mt7621-pci: release gpios after pci initializationSergio Paracuellos1-5/+18
R3G's LEDs fail to initialize because one of them uses GPIO8 Hence, release the GPIO resources after PCIe initialization and properly release also in driver error path. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200313200913.24321-6-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-17staging: mt7621-pci: bindings: update doc accordly to last changesSergio Paracuellos1-2/+5
Properly update bindings documentation with added 'reset-gpios' property. Delete also 'perst-gpio' which is not being used anymore. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200313200913.24321-5-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-17staging: mt7621-pci: change value for 'PERST_DELAY_MS'Sergio Paracuellos1-3/+3
Value of 'PERST_DELAY_MS' is too high and it is ok just to set up to 100 ms. Update also define name from 'PERST_DELAY_US' into 'PERST_DELAY_MS' Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200313200913.24321-3-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-17staging: mt7621-pci: use gpios for properly resetSergio Paracuellos1-33/+51
Original driver code was using three gpio's for reset asserts and deasserts the pcis. Instead of using that a general reset control with a perst gpio was introduced and it seems it is partially working but sometimes there are some unexpected hangs on boot. This commit make use of the three original gpios using 'reset-gpios' property of the device tree and removes the reset line and perst gpio. According to the mediatek aplication note v0.1 there are three gpios used for pcie ports reset control: gpio#19, gpio#8 and gpio#7 for slots 0, 1 and 2 respectively. This schema can be used separately for mt7621A but in some boards due to pin share issue, if the PCM and I2S function are enable at the same time, there are no enough GPIO to control per-port PCIe reset. In those cases gpio#19 is enought for reset the three ports together. Because of this we just try to get the three gpios but if some of them fail we are not failing in boot process, just prints a kernel notice and take after into account if the descriptor is or not valid in order to use it. All of them are set as GPIO output low configuration. The gpio descriptor's API takes device tree property into account and invert value if the pin is configured as active low. So we also have to properly request pins from device tree and set values correct in assert and deassert functions. After this changes the order to make all assert and deassert in the 'probe' process makes more sense: * Parse device tree. * make assert of the RC's and EP's before doing anything else. * make deassert of the RC's before initializing the phy. * Init the phy. * make deassert of the EP's before initialize pci ports. * Normal PCI initialization. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200313200913.24321-2-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-03-11staging: mt7621-pci: enable clock bit for each portSergio Paracuellos1-11/+6
The clock related code concerns me from the very beginning because there are some set ups got from legacy driver that are not documented anywhere. According to the programming guide 0x7c is 'CPE_ROSC_SEL1' register and 0x80 is 'CPU_CPE_CN'. I do think this set up is not needed at all and the proper thing to do is just enable the clock bit for each pcie port. Hence remove useless code and do the right thing which is setting up the clock bit for each port enabled. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200310113459.30539-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>