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| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2021-06-07 14:01:53 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-06-09 14:19:22 +0200 |
| commit | 25203e32ce3ef9bfa363cfed7813c4fd7270ce45 (patch) | |
| tree | ea30faf268a6e5daecb3ef4e7d15ed1129f6fb92 /drivers/staging/mt7621-pci | |
| parent | 2d3d288f0eaf102c3739ad811fa9727c742a49e0 (diff) | |
| download | linux-25203e32ce3ef9bfa363cfed7813c4fd7270ce45.tar.bz2 | |
staging: mt7621-pci: make use of 'pcie_port_write'
Function 'mt7621_pcie_enable_port' is calculating an offset
to write some port related registers. Instead of doing that
just make use of already existent 'pcie_write_port' function
and use virtualy mapped base address with registers. This
increase readability and allow us to remove also two defitions
not used else where.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210607120153.24989-7-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-pci')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index fe9a5bb95d5b..b0b5700cbfec 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -44,9 +44,6 @@ #define RALINK_PCI_IOBASE 0x002C /* PCIe RC control registers */ -#define MT7621_PCIE_OFFSET 0x2000 -#define MT7621_NEXT_PORT 0x1000 - #define RALINK_PCI_ID 0x0030 #define RALINK_PCI_CLASS 0x0034 #define RALINK_PCI_SUBID 0x0038 @@ -491,7 +488,6 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) { struct mt7621_pcie *pcie = port->pcie; u32 slot = port->slot; - u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT); u32 val; /* enable pcie interrupt */ @@ -500,12 +496,12 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR); /* map 2G DDR region */ - pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, - offset + PCI_BASE_ADDRESS_0); + pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, + PCI_BASE_ADDRESS_0); /* configure class code and revision ID */ - pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID, - offset + RALINK_PCI_CLASS); + pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID, + RALINK_PCI_CLASS); /* configure RC FTS number to 250 when it leaves L0s */ val = read_config(pcie, slot, PCIE_FTS_NUM); |