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path: root/drivers/spi
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2020-10-08spi: dw: Move num-of retries parameter to the header fileSerge Semin2-3/+4
2020-10-08spi: dw: Explicitly de-assert CS on SPI transfer completionSerge Semin1-1/+1
2020-10-08spi: dw: De-assert chip-select on resetSerge Semin1-3/+4
2020-10-08spi: dw: Discard chip enabling on DMA setup errorSerge Semin1-3/+1
2020-10-08spi: dw: Unmask IRQs after enabling the chipSerge Semin1-2/+2
2020-10-08spi: dw: Perform IRQ setup in a dedicated functionSerge Semin1-18/+23
2020-10-08spi: dw: Refactor IRQ-based SPI transfer procedureSerge Semin1-9/+24
2020-10-08spi: dw: Refactor data IO procedureSerge Semin2-23/+19
2020-10-08spi: dw: Add DW SPI controller config structureSerge Semin2-12/+27
2020-10-08spi: dw: Update Rx sample delay in the config functionSerge Semin1-7/+6
2020-10-08spi: dw: Simplify the SPI bus speed config procedureSerge Semin1-13/+10
2020-10-08spi: dw: Update SPI bus speed in a config functionSerge Semin1-14/+14
2020-10-08spi: dw: Detach SPI device specific CR0 config methodSerge Semin1-13/+30
2020-10-08spi: dw: Add DWC SSI capabilitySerge Semin4-75/+40
2020-10-08spi: dw: Use an explicit set_cs assignmentSerge Semin1-4/+4
2020-10-06spi: spi-mtk-nor: Add power management supportIkjoon Jang1-22/+76
2020-10-06spi: spi-mtk-nor: support 36bit dma addressingIkjoon Jang1-1/+20
2020-10-06spi: spi-mtk-nor: use dma_alloc_coherent() for bounce bufferIkjoon Jang1-42/+52
2020-10-02spi: spi-s3c64xx: Turn on interrupts upon resumeŁukasz Stelmach1-0/+4
2020-10-02spi: spi-s3c64xx: Increase transfer timeoutŁukasz Stelmach1-1/+2
2020-10-02spi: spi-s3c64xx: Ensure cur_speed holds actual clock valueŁukasz Stelmach1-0/+1
2020-10-02spi: spi-s3c64xx: Fix doc comment for struct s3c64xx_spi_driver_dataŁukasz Stelmach1-4/+1
2020-10-02spi: spi-s3c64xx: Rename S3C64XX_SPI_SLAVE_* to S3C64XX_SPI_CS_*Łukasz Stelmach1-13/+13
2020-10-02spi: spi-s3c64xx: Report more information when errors occurŁukasz Stelmach1-4/+15
2020-10-02spi: spi-s3c64xx: Check return valuesŁukasz Stelmach1-9/+41
2020-10-02spi: spi-s3s64xx: Add S3C64XX_SPI_QUIRK_CS_AUTO for Exynos3250Łukasz Stelmach1-0/+1
2020-10-02spi: spi-s3c64xx: swap s3c64xx_spi_set_cs() and s3c64xx_enable_datapath()Łukasz Stelmach1-2/+2
2020-10-01Merge series "spi: spi-mtk-nor: make use of full capability of program mode" ...Mark Brown1-21/+158
2020-10-01spi: spi-stm32: remove redundant irqsave and irqrestore in hardIRQBarry Song1-5/+4
2020-10-01spi: spi-tegra20-sflash: remove redundant irqsave and irqrestore in hardIRQBarry Song1-3/+2
2020-10-01spi: atmel: Exposing effective spi speedThomas Kopp1-0/+1
2020-10-01spi: spi-mtk-nor: fix op checks in supports_opChuanhong Guo1-12/+9
2020-10-01spi: spi-mtk-nor: add helper for checking prg mode opsChuanhong Guo1-7/+69
2020-10-01spi: spi-mtk-nor: make use of full capability of prg modeChuanhong Guo1-2/+80
2020-09-29Merge series "spi: dw: Add full Baikal-T1 SPI Controllers support" from Serge...Mark Brown3-65/+42
2020-09-29spi: spi-dw: Remove extraneous lockingSerge Semin2-13/+2
2020-09-29spi: dw: Add KeemBay Master capabilitySerge Semin3-17/+15
2020-09-29spi: dw: Convert CS-override to DW SPI capabilitiesSerge Semin3-4/+9
2020-09-29spi: dw: Discard DW SSI chip type storagesSerge Semin2-5/+2
2020-09-29spi: dw: Use relaxed IO-methods to access FIFOsSerge Semin1-14/+4
2020-09-29spi: dw: Disable all IRQs when controller is unusedSerge Semin1-5/+5
2020-09-29spi: dw: Clear IRQ status on DW SPI controller resetSerge Semin1-3/+4
2020-09-29spi: dw: Initialize n_bytes before the memory barrierSerge Semin1-1/+1
2020-09-29spi: dw: Discard IRQ threshold macroSerge Semin1-3/+0
2020-09-29spi: dw-dma: Add one-by-one SG list entries transferSerge Semin2-1/+137
2020-09-29spi: dw-dma: Pass exact data to the DMA submit and wait methodsSerge Semin1-18/+17
2020-09-29spi: dw-dma: Move DMAC register cleanup to DMA transfer methodSerge Semin1-9/+8
2020-09-29spi: dw-dma: Detach DMA transfer into a dedicated methodSerge Semin1-2/+10
2020-09-29spi: dw-dma: Remove DMA Tx-desc passing aroundSerge Semin1-17/+14
2020-09-29spi: dw-dma: Check DMA Tx-desc submission statusSerge Semin1-2/+18
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