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path:
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drivers
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spi
/
spi-dw-dma.c
Age
Commit message (
Expand
)
Author
Files
Lines
2022-11-16
spi: dw-dma: decrease reference count in dw_spi_dma_init_mfld()
Xiongfeng Wang
1
-0
/
+3
2022-06-27
spi: dw: Add deferred DMA-channels setup support
Serge Semin
1
-7
/
+18
2021-11-16
spi: dw: Put the driver entities naming in order
Serge Semin
1
-25
/
+25
2021-11-16
spi: dw: Add a symbols namespace for the core module
Serge Semin
1
-2
/
+3
2020-10-08
spi: dw: Add generic DW SSI status-check method
Serge Semin
1
-9
/
+2
2020-10-08
spi: dw: Move num-of retries parameter to the header file
Serge Semin
1
-3
/
+2
2020-09-29
spi: dw-dma: Add one-by-one SG list entries transfer
Serge Semin
1
-1
/
+136
2020-09-29
spi: dw-dma: Pass exact data to the DMA submit and wait methods
Serge Semin
1
-18
/
+17
2020-09-29
spi: dw-dma: Move DMAC register cleanup to DMA transfer method
Serge Semin
1
-9
/
+8
2020-09-29
spi: dw-dma: Detach DMA transfer into a dedicated method
Serge Semin
1
-2
/
+10
2020-09-29
spi: dw-dma: Remove DMA Tx-desc passing around
Serge Semin
1
-17
/
+14
2020-09-29
spi: dw-dma: Check DMA Tx-desc submission status
Serge Semin
1
-2
/
+18
2020-09-29
spi: dw-dma: Move DMA transfers submission to the channels prep methods
Serge Semin
1
-10
/
+12
2020-09-29
spi: dw-dma: Check rx_buf availability in the xfer method
Serge Semin
1
-7
/
+6
2020-09-29
spi: dw-dma: Configure the DMA channels in dma_setup
Serge Semin
1
-11
/
+31
2020-09-29
spi: dw-dma: Fail DMA-based transfer if no Tx-buffer specified
Serge Semin
1
-14
/
+13
2020-09-29
spi: dw-dma: Set DMA Level registers on init
Serge Semin
1
-15
/
+13
2020-07-21
spi: dw-dma: Fix Tx DMA channel working too fast
Serge Semin
1
-1
/
+13
2020-05-29
spi: dw: Refactor mid_spi_dma_setup() to separate DMA and IRQ config
Andy Shevchenko
1
-6
/
+6
2020-05-29
spi: dw: Make DMA request line assignments explicit for Intel Medfield
Andy Shevchenko
1
-8
/
+6
2020-05-29
spi: dw: Cleanup generic DW DMA code namings
Serge Semin
1
-42
/
+43
2020-05-29
spi: dw: Move Non-DMA code to the DW PCIe-SPI driver
Serge Semin
1
-0
/
+481