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path:
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drivers
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pinctrl
/
aspeed
Age
Commit message (
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Author
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2017-01-26
pinctrl: aspeed: g4: Fix mux configuration for GPIOs AA[4-7], AB[0-7]
Andrew Jeffery
1
-16
/
+16
2016-12-28
pinctrl: aspeed: Fix kerneldoc return descriptions
Andrew Jeffery
1
-6
/
+6
2016-12-28
pinctrl: aspeed-g5: Add mux configuration for all pins
Andrew Jeffery
2
-4
/
+1475
2016-12-27
pinctrl: aspeed-g4: Add mux configuration for all pins
Andrew Jeffery
1
-13
/
+1084
2016-12-27
pinctrl: aspeed: Read and write bits in LPC and GFX controllers
Andrew Jeffery
4
-88
/
+171
2016-11-07
pinctrl-aspeed-g5: Never set SCU90[6]
Andrew Jeffery
1
-1
/
+1
2016-10-18
pinctrl: aspeed-g5: Fix pin association of SPI1 function
Andrew Jeffery
1
-8
/
+78
2016-10-18
pinctrl: aspeed-g5: Fix GPIOE1 typo
Andrew Jeffery
1
-1
/
+1
2016-10-18
pinctrl: aspeed-g5: Fix names of GPID2 pins
Andrew Jeffery
1
-6
/
+6
2016-10-18
pinctrl: aspeed: "Not enabled" is a significant mux state
Andrew Jeffery
1
-5
/
+7
2016-09-13
pinctrl: aspeed: fix regmap error handling
Arnd Bergmann
1
-3
/
+3
2016-09-07
pinctrl: Add pinctrl-aspeed-g5 driver
Andrew Jeffery
3
-0
/
+817
2016-09-07
pinctrl: Add pinctrl-aspeed-g4 driver
Andrew Jeffery
3
-0
/
+1240
2016-09-07
pinctrl: Add core support for Aspeed SoCs
Andrew Jeffery
4
-0
/
+1079