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path: root/drivers/phy/mediatek
AgeCommit message (Expand)AuthorFilesLines
2020-03-20phy: phy-mtk-tphy: add a new reference clockChunfeng Yun1-1/+18
2020-03-20phy: phy-mtk-tphy: remove unused u3phya_ref clockChunfeng Yun1-18/+0
2020-03-20phy: phy-mtk-tphy: make the ref clock optionalChunfeng Yun1-1/+1
2020-03-20phy: phy-mtk-tphy: add a property for internal resistanceChunfeng Yun1-2/+14
2020-03-20phy: phy-mtk-tphy: add a property for disconnect thresholdChunfeng Yun1-2/+15
2020-01-14phy: Enable compile testing for some of driversKrzysztof Kozlowski1-3/+6
2020-01-14phy: mediatek: Fix Kconfig indentationKrzysztof Kozlowski1-10/+10
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2019-04-18scsi: phy: mediatek: fix typo in author's email addressColin Ian King1-1/+1
2019-04-17phy: phy-mtk-tphy: get optional clock by devm_clk_get_optional()Chunfeng Yun1-7/+3
2019-04-17phy: mediatek: Add UFS M-PHY driverStanley Chu3-0/+256
2018-12-12phy: core: rework phy_set_mode to accept phy mode and submodeGrygorii Strashko2-2/+2
2018-07-10phy: phy-mtk-tphy: add property for BC12Chunfeng Yun1-0/+13
2018-07-10phy: phy-mtk-tphy: add properties for eye diagram testChunfeng Yun1-0/+62
2018-07-10phy: phy-mtk-tphy: use SPDX license tagChunfeng Yun2-9/+2
2018-05-20phy: mediatek: add XS-PHY driverChunfeng Yun3-0/+610
2018-03-16phy: phy-mtk-tphy: add configurable parameters for slew rate calibrateChunfeng Yun1-5/+15
2018-03-16phy: phy-mtk-tphy: keep default value of mcu_bus_ck_gate_enChunfeng Yun1-2/+1
2017-12-29phy: phy-mtk-tphy: use of_device_get_match_data()Chunfeng Yun1-6/+5
2017-12-29phy: phy-mtk-tphy: make shared banks optional for V1 TPHYChunfeng Yun1-2/+3
2017-12-29phy: phy-mtk-tphy: use auto instead of force to bypass utmi signalsChunfeng Yun1-12/+7
2017-10-23phy: phy-mtk-tphy: add set_mode callbackChunfeng Yun1-0/+39
2017-09-26phy: phy-mtk-tphy: fix NULL point of chip bankChunfeng Yun1-1/+2
2017-08-20phy: phy-mt65xx-usb3: add mediatek directory and rename fileChunfeng Yun3-0/+1100