summaryrefslogtreecommitdiffstats
path: root/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
AgeCommit message (Expand)AuthorFilesLines
2022-04-06net: axiemac: use a phandle to reference pcs_phyAndy Chiu1-2/+9
2022-04-06net: axienet: factor out phy_node in struct axienet_localAndy Chiu1-8/+5
2022-04-06net: axienet: setup mdio unconditionallyAndy Chiu1-7/+6
2022-03-09net: axienet: Use napi_alloc_skb when refilling RX ringRobert Hancock1-1/+1
2022-03-05net: axienet: add coalesce timer ethtool configurationRobert Hancock1-11/+40
2022-03-05net: axienet: implement NAPI and GRO receiveRobert Hancock1-28/+53
2022-03-05net: axienet: don't set IRQ timer when IRQ delay not usedRobert Hancock1-4/+14
2022-03-05net: axienet: Clean up DMA start/stop and error handlingRobert Hancock1-175/+105
2022-03-05net: axienet: Clean up device used for DMA callsRobert Hancock1-16/+16
2022-03-05net: axienet: fix RX ring refill allocation failure handlingRobert Hancock1-30/+42
2022-02-18net: ethernet: xilinx: cleanup commentsTom Rix1-1/+1
2022-01-26net: axienet: replace mdiobus_write() with mdiodev_write()Russell King (Oracle)1-2/+1
2022-01-26net: axienet: convert to phylink_pcsRussell King (Oracle)1-54/+53
2022-01-19net: axienet: increase default TX ring size to 128Robert Hancock1-1/+1
2022-01-19net: axienet: fix for TX busy handlingRobert Hancock1-39/+47
2022-01-19net: axienet: fix number of TX ring slots for available checkRobert Hancock1-2/+2
2022-01-19net: axienet: Fix TX ring slot available checkRobert Hancock1-2/+2
2022-01-19net: axienet: limit minimum TX ring sizeRobert Hancock1-1/+3
2022-01-19net: axienet: add missing memory barriersRobert Hancock1-1/+10
2022-01-19net: axienet: reset core on initialization prior to MDIO accessRobert Hancock1-0/+5
2022-01-19net: axienet: Wait for PhyRstCmplt after core resetRobert Hancock1-0/+10
2022-01-19net: axienet: increase reset timeoutRobert Hancock1-10/+9
2021-12-13net: axienet: mark as a legacy_pre_march2020 driverRussell King (Oracle)1-0/+1
2021-11-22ethtool: extend ringparam setting/getting API with rx_buf_lenHao Chen1-4/+10
2021-11-17net: axienet: use phylink_generic_validate()Russell King (Oracle)1-38/+3
2021-11-17net: axienet: remove interface checks in axienet_validate()Russell King (Oracle)1-22/+0
2021-11-17net: axienet: populate supported_interfaces memberRussell King (Oracle)1-0/+8
2021-10-24net: convert users of bitmap_foo() to linkmode_foo()Sean Anderson1-5/+3
2021-10-02ethernet: use eth_hw_addr_set()Jakub Kicinski1-1/+1
2021-08-24ethtool: extend coalesce setting uAPI with CQE modeYufeng Mo1-4/+14
2021-07-27dev_ioctl: split out ndo_eth_ioctlArnd Bergmann1-1/+1
2021-06-10net: axienet: Use devm_platform_get_and_ioremap_resource()Yang Yingliang1-5/+2
2021-05-30net: axienet: Fix fall-through warning for ClangGustavo A. R. Silva1-0/+1
2021-04-13of: net: pass the dst buffer to of_get_mac_address()Michael Walle1-7/+8
2021-04-09Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-6/+6
2021-03-29net: axienet: Remove redundant dev_err call in axienet_probe()Guobin Huang1-1/+0
2021-03-26net: axienet: Enable more clocksRobert Hancock1-7/+27
2021-03-25net: axienet: allow setups without MDIODaniel Mack1-6/+6
2021-03-12net: axienet: Fix probe error cleanupRobert Hancock1-12/+25
2021-02-16Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netDavid S. Miller1-14/+12
2021-02-12net: axienet: Support dynamic switching between 1000BaseX and SGMIIRobert Hancock1-7/+53
2021-02-12net: axienet: hook up nway_reset ethtool operationRobert Hancock1-0/+8
2021-02-12net: axienet: Handle deferred probe on clock properlyRobert Hancock1-14/+12
2020-11-07net: xilinx: axiethernet: Enable dynamic MDIO MDCClayton Rayment1-17/+4
2020-10-31net: axienet: Properly handle PCS/PMA PHY for 1000BaseX modeRobert Hancock1-26/+68
2020-09-07net: xilinx: remove redundant null check before clk_disable_unprepare()Zhang Changzhong1-2/+1
2020-03-24net: axienet: Allow DMA to beyond 4GBAndre Przywara1-0/+8
2020-03-24net: axienet: Autodetect 64-bit DMA capabilityAndre Przywara1-0/+26
2020-03-24net: axienet: Upgrade descriptors to hold 64-bit addressesAndre Przywara1-35/+78
2020-03-24net: axienet: Wrap DMA pointer writes to prepare for 64 bitAndre Przywara1-10/+16
generated by cgit v1.2.3 (git 2.39.1) at 2025-03-07 11:37:30 +0000