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2017-10-10mmc: sdhci-pci: Fix default d3_retune for Intel host controllersAdrian Hunter1-0/+2
The default for d3_retune is true, but that was not being set in all cases, which results in eMMC errors because re-tuning has not been done. Fix by initializing d3_retune to true. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: c959a6b00ff5 ("mmc: sdhci-pci: Don't re-tune with runtime pm for some Intel devices") Cc: stable@vger.kernel.org # v4.12+ Reported-and-tested-by: ojab <ojab@ojab.ru> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-10-04mmc: sdhci-xenon: Fix clock resource by adding an optional bus clockGregory CLEMENT2-4/+21
On Armada 7K/8K we need to explicitly enable the bus clock. The bus clock is optional because not all the SoCs need them but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updating accordingly. Without this patch the kernel hand during boot if the mvpp2.2 network driver was not present in the kernel. Indeed the clock needed by the xenon controller was set by the network driver. Fixes: 3a3748dba881 ("mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality)" CC: Stable <stable@vger.kernel.org> Tested-by: Zhoujie Wu <zjwu@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-10-04mmc: meson-gx: include tx phase in the tuning processJerome Brunet1-1/+18
It has been reported that some platforms (odroid-c2) may require a different tx phase setting to operate at high speed (hs200 and hs400) To improve the situation, this patch includes tx phase in the tuning process. Fixes: d341ca88eead ("mmc: meson-gx: rework tuning function") Reported-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-10-04mmc: meson-gx: fix rx phase resetJerome Brunet1-2/+4
Resetting the phase when POWER_ON is set the set_ios() call means that the phase is reset almost every time the set_ios() is called, while the expected behavior was to reset the phase on a power cycle. This had gone unnoticed until now because in all mode (except hs400) the tuning is done after the last to set_ios(). In such case, the tuning result is used anyway. In HS400, there are a few calls to set_ios() after the tuning is done, overwriting the tuning result. Resetting the phase on POWER_UP instead of POWER_ON solve the problem. Fixes: d341ca88eead ("mmc: meson-gx: rework tuning function") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-10-04mmc: meson-gx: make sure the clock is rounded downJerome Brunet1-2/+1
Using CLK_DIVIDER_ROUND_CLOSEST is unsafe as the mmc clock could be rounded to a rate higher the specified rate. Removing this flag ensure that, if the rate needs to be rounded, it will be rounded down. Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-10-04mmc: Delete bounce buffer handlingLinus Walleij5-131/+11
In may, Steven sent a patch deleting the bounce buffer handling and the CONFIG_MMC_BLOCK_BOUNCE option. I chose the less invasive path of making it a runtime config option, and we merged that successfully for kernel v4.12. The code is however just standing in the way and taking up space for seemingly no gain on any systems in wide use today. Pierre says the code was there to improve speed on TI SDHCI controllers on certain HP laptops and possibly some Ricoh controllers as well. Early SDHCI controllers lacked the scatter-gather feature, which made software bounce buffers a significant speed boost. We are clearly talking about the list of SDHCI PCI-based MMC/SD card readers found in the pci_ids[] list in drivers/mmc/host/sdhci-pci-core.c. The TI SDHCI derivative is not supported by the upstream kernel. This leaves the Ricoh. What we can however notice is that the x86 defconfigs in the kernel did not enable CONFIG_MMC_BLOCK_BOUNCE option, which means that any such laptop would have to have a custom configured kernel to actually take advantage of this bounce buffer speed-up. It simply seems like there was a speed optimization for the Ricoh controllers that noone was using. (I have not checked the distro defconfigs but I am pretty sure the situation is the same there.) Bounce buffers increased performance on the OMAP HSMMC at one point, and was part of the original submission in commit a45c6cb81647 ("[ARM] 5369/1: omap mmc: Add new omap hsmmc controller for 2430 and 34xx, v3") This optimization was removed in commit 0ccd76d4c236 ("omap_hsmmc: Implement scatter-gather emulation") which found that scatter-gather emulation provided even better performance. The same was introduced for SDHCI in commit 2134a922c6e7 ("sdhci: scatter-gather (ADMA) support") I am pretty positively convinced that software scatter-gather emulation will do for any host controller what the bounce buffers were doing. Essentially, the bounce buffer was a reimplementation of software scatter-gather-emulation in the MMC subsystem, and it should be done away with. Cc: Pierre Ossman <pierre@ossman.eu> Cc: Juha Yrjola <juha.yrjola@solidboot.com> Cc: Steven J. Hill <Steven.Hill@cavium.com> Cc: Shawn Lin <shawn.lin@rock-chips.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Suggested-by: Steven J. Hill <Steven.Hill@cavium.com> Suggested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-10-02mmc: core: add driver strength selection when selecting hs400esChanho Min1-17/+19
The driver strength selection is missed and required when selecting hs400es. So, It is added here. Fixes: 81ac2af65793ecf ("mmc: core: implement enhanced strobe support") Cc: stable@vger.kernel.org Signed-off-by: Hankyung Yu <hankyung.yu@lge.com> Signed-off-by: Chanho Min <chanho.min@lge.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-09-26Merge tag 'mmc-v4.14-rc1' of ↵Linus Torvalds2-47/+15
git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC fixes from Ulf Hansson: - sdhci-pci: Fix voltage switch for some Intel host controllers - tmio: remove broken and noisy debug macro * tag 'mmc-v4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci-pci: Fix voltage switch for some Intel host controllers mmc: tmio: remove broken and noisy debug macro
2017-09-22mmc: sdhci-pci: Fix voltage switch for some Intel host controllersAdrian Hunter1-0/+15
Some Intel host controllers (e.g. CNP) use an ACPI device-specific method to ensure correct voltage switching. Fix voltage switch for those, by adding a call to the DSM. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-09-22mmc: tmio: remove broken and noisy debug macroWolfram Sang1-47/+0
Some change for v4.14 broke the debug output for TMIO. But since it was not helpful to me and too noisy for my taste anyhow, let's just remove it instead of fixing it. We'll find something better if we'd need it... Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-09-08mmc: cavium: Fix use-after-free in of_platform_device_destroyJan Glauber1-1/+5
KASAN reported the following: [ 19.338655] ================================================================== [ 19.345946] BUG: KASAN: use-after-free in of_platform_device_destroy+0x88/0x100 [ 19.345966] Read of size 8 at addr fffffe01aa6f1468 by task systemd-udevd/264 [ 19.345983] CPU: 1 PID: 264 Comm: systemd-udevd Not tainted 4.13.0-jang+ #737 [ 19.345989] Hardware name: Cavium ThunderX CN81XX board (DT) [ 19.345995] Call trace: [ 19.346013] [<fffffc800808b1b0>] dump_backtrace+0x0/0x368 [ 19.346026] [<fffffc800808b6bc>] show_stack+0x24/0x30 [ 19.346040] [<fffffc8008cbb944>] dump_stack+0xa4/0xc8 [ 19.346057] [<fffffc80082c2870>] print_address_description+0x68/0x258 [ 19.346070] [<fffffc80082c2d70>] kasan_report+0x238/0x2f8 [ 19.346082] [<fffffc80082c14a8>] __asan_load8+0x88/0xb8 [ 19.346098] [<fffffc8008aacee0>] of_platform_device_destroy+0x88/0x100 [ 19.346131] [<fffffc8000e02fa4>] thunder_mmc_probe+0x314/0x550 [thunderx_mmc] [ 19.346147] [<fffffc800879d560>] pci_device_probe+0x158/0x1f8 [ 19.346162] [<fffffc800886e53c>] driver_probe_device+0x394/0x5f8 [ 19.346174] [<fffffc800886e8f4>] __driver_attach+0x154/0x158 [ 19.346185] [<fffffc800886b12c>] bus_for_each_dev+0xdc/0x140 [ 19.346196] [<fffffc800886d9f8>] driver_attach+0x38/0x48 [ 19.346207] [<fffffc800886d148>] bus_add_driver+0x290/0x3c8 [ 19.346219] [<fffffc800886fc5c>] driver_register+0xbc/0x1a0 [ 19.346232] [<fffffc800879b78c>] __pci_register_driver+0xc4/0xd8 [ 19.346260] [<fffffc8000e80024>] thunder_mmc_driver_init+0x24/0x10000 [thunderx_mmc] [ 19.346273] [<fffffc8008083a80>] do_one_initcall+0x98/0x1c0 [ 19.346289] [<fffffc8008177b54>] do_init_module+0xe0/0x2cc [ 19.346303] [<fffffc8008175cf0>] load_module+0x3238/0x35c0 [ 19.346318] [<fffffc8008176438>] SyS_finit_module+0x190/0x1a0 [ 19.346329] [<fffffc80080834a0>] __sys_trace_return+0x0/0x4 This is caused by: platform_device_register() -> platform_device_unregister(to_platform_device(dev)) freeing struct device -> of_node_clear_flag(dev->of_node, ...) writing to the freed device The issue is solved by increasing the reference count before calling of_platform_device_destroy() so freeing the device is postponed after the call. Fixes: 8fb83b142823 ("mmc: cavium: Fix probing race with regulator") Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-09-08mmc: host: fix typo after MMC_DEBUG moveWolfram Sang1-1/+1
MMC_DEBUG was moved and one letter got strangely capitalized. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-09-08mmc: block: Fix incorrectly initialized requestsAdrian Hunter1-1/+6
mmc_init_request() depends on card->bouncesz so it must be calculated before blk_init_allocated_queue() starts allocating requests. Reported-by: Seraphime Kirkovski <kirkseraph@gmail.com> Fixes: 304419d8a7e9 ("mmc: core: Allocate per-request data using the..") Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Seraphime Kirkovski <kirkseraph@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Pavel Machek <pavel@ucw.cz>
2017-09-01mmc: renesas_sdhi: Add r8a7743/5 supportBiju Das1-0/+2
Add support for r8a7743/5 SoC.Renesas RZ/G1[ME] (R8A7743/5) SDHI is identical to the R-Car Gen2 family. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-31mmc: meson-gx: fix __ffsdi2 undefined on arm32Jerome Brunet1-7/+7
Using __bf_shf does not compile on arm 32 architecture. This has gone unnoticed till now cause the driver is only used on arm64. In addition, __bf_shf was already used in the driver without any issue. It was used on a constant value, so the call was probably optimized away. Replace __bf_shf by __ffs fixes the problem Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-xenon: add runtime pm support and reimplement standbyZhoujie Wu2-16/+72
Enable runtime pm support for xenon controller, which uses 50ms auto runtime suspend by default. Reimplement system standby based on runtime pm API. Introduce restore_needed to restore the Xenon specific registers when resume. Signed-off-by: Zhoujie Wu <zjwu@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30Merge branch 'fixes' into nextUlf Hansson2-3/+22
2017-08-30mmc: core: Move mmc_start_areq() declarationAdrian Hunter1-0/+6
mmc_start_areq() is an internal mmc core API. Move the declaration accordingly. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: mmci: stop building qcom dml as moduleSrinivas Kandagatla2-3/+4
It does not make sense for qcom dml code to be a seperate module, as this has just 2 helper functions specific to qcom, and used directly by mmci driver, so just compile this along with main mmci driver. This would also fix issues arrising due to Kconfig combinations between mmci and qcom dml. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sunxi: Reset the device at probe timeMaxime Ripard1-1/+1
We might be into some troubles if the bootloader misconfigured the MMC controller. We currently only de-assert the reset line at probe time, which means that if the device was already out of reset, we're going to keep whatever state was set already. Switch to a reset instead of the deassert to have a device in a pristine state when we start operating. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: rework tuning functionJerome Brunet1-50/+111
Rework tuning function of the rx phase. Now that the phase can be more precisely set using CCF, test more phase setting and find the largest working window. Then the tuning selected is the one at the center of the window. This rework allows to use new modes, such as UHS SDR50 Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: change default tx phaseJerome Brunet1-1/+7
Initial default tx phase was set to 0 while the datasheet recommends 270. Some cards fails to initialize with this setting and eMMC mode DDR52 does not work. Changing this setting to 270 fixes these issues, without any regression so far Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: implement voltage switch callbackJerome Brunet1-0/+22
Implement voltage switch callback (shamelessly copied from sunxi mmc driver). This allow, with the appropriate tuning function, to use SD ultra high speed modes. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: use CCF to handle the clock phasesJerome Brunet1-41/+176
Several phases can be controlled on the meson-gx controller, the core, tx and rx clock phase. The tx and rx uses delays to allow more fine grained setting of the phase. To properly compute the phase using delays, accessing the clock rate is necessary. Instead of ad-hoc functions, use the common clock framework to set the clock phases (and access the clock rate while doing it). Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: implement card_busy callbackJerome Brunet1-0/+13
Implement the card_busy callback to be able to verify that the card is done dealing with voltage switch, when the support is added later on. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: simplify interrupt handlerJerome Brunet1-54/+39
No functional change, just improve interrupt handler readability Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: work around clk-stop issueJerome Brunet1-6/+68
It seems that the mmc clock is also used and required, somehow, by the controller itself. It is shown during init, when writing to CFG while the divider is set to 0 will crash the SoC. During a voltage switch, the controller may crash and the card may then fail to exit busy state if the clock is stopped. To avoid this, it is best to keep the clock running for the controller, except during rate change. However, we still need to be able to gate the clock out of the SoC. Let's use the pinmux for this, and fallback to gpio mode (pulled-down) when we need to gate the clock Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: fix dual data rate mode frequenciesJerome Brunet1-12/+29
In DDR modes, meson mmc controller requires an input rate twice as fast as the output rate Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: rework clock init functionJerome Brunet1-48/+46
Thanks to devm, carrying the clock structure around after init is not necessary. Rework the function to remove these from the controller host data. Finally, set initial mmc clock rate before enabling it, simplifying the exit condition. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: rework clk_set functionJerome Brunet1-21/+9
Clean-up clk_set function to prepare the next changes (DDR and clk-stop) Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: rework set_ios functionJerome Brunet1-13/+9
Remove conditional write of cfg register. Warn if set_clk fails for some reason. Consistently use host->dev instead of mixing with mmc_dev(mmc) Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: cfg init overwrite valuesJerome Brunet1-10/+4
cfg init function overwrite values set in the clk init function Remove the cfg pokes from the clk init. Actually, trying to use the CLK_AUTO, like initially tried in clk_init, would break the card initialization Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: initialize sane clk default before clock registerJerome Brunet1-10/+9
On boot, the clock divider value is 0 which is a weird unsupported value. For example, accessing the cfg register with this value set would crash the SoC. Previous change removed 0 as possible value for CCF but forgot to properly initialize the register before registering the clock. This leads to the CCF finding an illegal value, which it complains about. Initialize the register properly in a standalone patch so the fix can be picked up if necessary. The change this fixed is: "mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag". Reported-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: mmci: constify amba_idArvind Yadav1-1/+1
amba_id are not supposed to change at runtime. All functions working with const amba_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: block: cast a informative log for no devidx availableShawn Lin1-1/+13
The intention for this patch is to help folks debug the failure like this: dwmmc_rockchip fe320000.dwmmc: IDMAC supports 32-bit address mode. dwmmc_rockchip fe320000.dwmmc: Using internal DMA controller. dwmmc_rockchip fe320000.dwmmc: Version ID is 270a dwmmc_rockchip fe320000.dwmmc: DW MMC controller at irq 28,32 bit host data width,256 deep fifo dwmmc_rockchip fe320000.dwmmc: Got CD GPIO mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0) mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) mmc0: new high speed SDHC card at address 0007 mmcblk: probe of mmc0:0007 failed with error -28 The reason may be some buggy userspace daemon miss the disk remove uevent sometimes so it would finally make the SD card not work. So from the dmesg it only shows a errno of -28 but still don't understand what happened. For quick reproduce this, we could set max_devices to 8 and run for i in $(seq 1 9); do echo "========================" $i echo fe320000.dwmmc > /sys/bus/platform/drivers/dwmmc_rockchip/unbind sleep .5 echo fe320000.dwmmc > /sys/bus/platform/drivers/dwmmc_rockchip/bind sleep .5 mount -t vfat /dev/mmcblk0 /mnt sleep .5 done Another possible reason would be the device has more partitions than what we support, so that they have to increase their max_devices. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-pltfm: export sdhci_pltfm_suspend/resumeMasahiro Yamada3-21/+7
This will be useful when drivers want to reuse either suspend or resume callback instead of whole of sdhci_pltfm_pmops. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci: enable/disable the clock in sdhci_pltfm_suspend/resumeMasahiro Yamada3-76/+22
This commit provides similar cleanups as commit 83eacdfa2529 ("mmc: sdhci: disable the clock in sdhci_pltfm_unregister()") did for unregister hooks. sdhci-brcmstb.c and sdhci-sirf.c implement their own suspend/resume hooks to handle pltfm_host->clk. Move clock handling to sdhci_pltfm.c so that the drivers can reuse sdhci_pltfm_pmops. The following drivers did not previously touch pltfm_host->clk during suspend/resume, but now do: - sdhci-bcm-kona.c - sdhci-dove.c - sdhci-iproc.c - sdhci-pxav2.c - sdhci-tegra.c - sdhci-xenon.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Al Cooper <alcooperx@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-pxav2: switch to managed clk and sdhci_pltfm_unregister()Masahiro Yamada1-23/+7
The difference between sdhci_pxav2_remove() and sdhci_pltfm_unregister() is clk_put(). It will go away by using the managed resource clk, then sdhci_pltfm_unregister() can be reused. Also, rename the jump labels to say what the goto does. (Coding style suggested by Documentation/process/coding-style.rst) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-cadence: add suspend / resume supportMasahiro Yamada1-9/+97
Currently, the probe function initializes the PHY, but PHY settings are lost during the sleep state. Restore the PHY registers when resuming. To facilitate this, split sdhci_cdns_phy_init() into the DT parse part and PHY update part so that the latter can be invoked from the resume hook. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-xenon: Support HS400 Enhanced Strobe featureHu Ziji2-6/+29
Support HS400 Enhanced Strobe feature in Xenon. Enable Enhanced Strobe together with Data Strobe. Disable Enhanced Strobe when eMMC is not in HS400 mode. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Zhoujie Wu <zjwu@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci: Add quirk to indicate MMC_RSP_136 has CRCKishon Vijay Abraham I2-0/+5
TI's implementation of sdhci controller used in DRA7 SoC's has CRC in responses with length 136 bits. Add quirk to indicate the controller has CRC in MMC_RSP_136. If this quirk is set sdhci library shouldn't shift the response present in SDHCI_RESPONSE register. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci: Tidy reading 136-bit responsesAdrian Hunter1-10/+18
Read each register only once and move the code to a separate function so that it is not jammed against the 80 column margin. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: clean up some constantsJerome Brunet1-3/+1
Remove unused clock rate defines. These should not be defined but requested from the clock framework. Also correct typo on the DELAY register Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flagJerome Brunet1-1/+1
Remove CLK_DIVIDER_ALLOW_ZERO. This flag means that a 1 based divider with a 0 value will behave as a bypass clock The mmc divider does not behave like this, a 0 value disables the clock Remove this flag so CCF never allows a 0 value on this clock Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: fix mux mask definitionJerome Brunet1-1/+1
CCF generic mux will shift the mask using the value defined in shift Define the mask accordingly Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: block: Reparametrize mmc_blk_ioctl_[multi]_cmd()Linus Walleij1-25/+18
Instead of passing a block device to mmc_blk_ioctl[_multi]_cmd(), let's pass struct mmc_blk_data() so we operate ioctl()s on the MMC block device representation rather than the vanilla block device. This saves a little duplicated code and makes it possible to issue ioctl()s not targeted for a specific block device but rather for a specific partition/area. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: block: Refactor mmc_blk_part_switch()Linus Walleij1-12/+13
Instead of passing a struct mmc_blk_data * to mmc_blk_part_switch() let's pass the actual partition type we want to switch to. This is necessary in order not to have a block device with a backing mmc_blk_data and request queue and all for every hardware partition, such as RPMB. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: block: Move duplicate checkLinus Walleij1-16/+20
mmc_blk_ioctl() calls either mmc_blk_ioctl_cmd() or mmc_blk_ioctl_multi_cmd() and each of these make the same check. Factor it into a new helper function, call it on both branches of the switch() statement and save a chunk of duplicate code. Cc: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: debugfs: Move block debugfs into block moduleLinus Walleij3-89/+147
If we don't have the block layer enabled, we do not present card status and extcsd in the debugfs. Debugfs is not ABI, and maintaining files of no relevance for non-block devices comes at a high maintenance cost if we shall support it with the block layer compiled out. The debugfs entries suffer from all the same starvation issues as the other userspace things, under e.g. a heavy dd operation. The expected number of debugfs users utilizing these two debugfs files is already low as there is an ioctl() to get the same information using the mmc-tools, and of these few users the expected number of people using it on SDIO or combo cards are expected to be zero. It is therefore logical to move this over to the block layer when it is enabled, using the new custom requests and issue it using the block request queue. On the other hand it moves some debugfs code from debugfs.c and into block.c. Tested during heavy dd load by cat:in the status file. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: ops: export mmc_get_status()Linus Walleij1-0/+1
This function retrieves the status of the card with the default number of retries. Since the block layer wants to use this, and since the block layer is a loadable kernel module, we need to export this symbol. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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