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path: root/drivers/gpu
AgeCommit message (Expand)AuthorFilesLines
2020-09-07drm/vc4: crtc: Move the CRTC disable outMaxime Ripard1-12/+22
2020-09-07drm/vc4: hvs: Introduce a function to get the assigned FIFOMaxime Ripard2-0/+55
2020-09-07drm/vc4: hvs: Make the stop_channel function publicMaxime Ripard2-1/+2
2020-09-07drm/vc4: crtc: Clear the PixelValve FIFO during configurationMaxime Ripard1-1/+1
2020-09-07drm/vc4: crtc: Clear the PixelValve FIFO on disableMaxime Ripard1-2/+1
2020-09-07drm/vc4: crtc: Add a delay after disabling the PixelValve outputMaxime Ripard1-0/+18
2020-09-07drm/vc4: encoder: Add finer-grained encoder callbacksMaxime Ripard2-0/+26
2020-09-07drm/vc4: crtc: Move HVS channel init before the PV initialisationMaxime Ripard1-4/+4
2020-09-07drm/vc4: crtc: Remove redundant pixelvalve resetMaxime Ripard1-1/+0
2020-09-07drm/vc4: crtc: Remove mode_set_nofbMaxime Ripard1-6/+1
2020-09-07drm/vc4: hvs: Make sure our channel is resetMaxime Ripard1-0/+4
2020-09-07drm/vc4: crtc: Move the HVS gamma LUT setup to our init functionMaxime Ripard4-47/+16
2020-09-07drm/vc4: crtc: Move HVS init and close to a functionMaxime Ripard1-46/+58
2020-09-07drm/vc4: crtc: Move PV dump to config_pvMaxime Ripard1-14/+12
2020-09-07drm/vc4: crtc: Turn pixelvalve reset into a functionMaxime Ripard1-7/+13
2020-09-07drm/vc4: crtc: Disable color management for HVS5Maxime Ripard2-7/+12
2020-09-07drm/vc4: crtc: Add HDMI1 encoder typeMaxime Ripard1-0/+1
2020-09-07drm/vc4: crtc: Rename HDMI encoder type to HDMI0Maxime Ripard3-3/+3
2020-09-07drm/vc4: crtc: Add function to compute FIFO level bitsMaxime Ripard1-2/+10
2020-09-07drm/vc4: crtc: Add FIFO depth to vc4_crtc_dataMaxime Ripard2-3/+20
2020-09-07drm/vc4: crtc: Assign output to channel automaticallyMaxime Ripard6-26/+200
2020-09-07drm/vc4: kms: Convert to for_each_new_crtc_stateMaxime Ripard1-4/+6
2020-09-07drm/vc4: crtc: Enable and disable the PV in atomic_enable / disableMaxime Ripard1-3/+7
2020-09-07drm/vc4: crtc: Use local chan variableMaxime Ripard1-1/+1
2020-09-07drm/vc4: crtc: Rename HVS channel to outputMaxime Ripard4-8/+8
2020-09-07drm/vc4: crtc: Move the cob allocation outside of bindMaxime Ripard2-20/+17
2020-09-07drm/vc4: crtc: Use a shared interruptMaxime Ripard1-1/+3
2020-09-07drm/vc4: crtc: Deal with different number of pixel per clockMaxime Ripard2-7/+14
2020-09-07drm/vc4: plane: Create more planesMaxime Ripard1-1/+1
2020-09-07drm/vc4: plane: Optimize the LBM allocation sizeDave Stevenson1-4/+13
2020-09-07drm/vc4: plane: Change LBM alignment constraint on LBMDave Stevenson1-1/+3
2020-09-07drm/vc4: hvs: Boost the core clock during modesetMaxime Ripard3-0/+29
2020-09-07drm/vc4: Add support for the BCM2711 HVS5Dave Stevenson4-59/+240
2020-09-07drm/bridge: dw-mipi-dsi.c: Add VPG runtime config through debugfsAngelo Ribeiro1-8/+90
2020-09-07drm/bridge/synopsys: dsi: add support for non-continuous HS clockAntonio Borneo1-2/+7
2020-09-07drm/bridge/synopsys: dsi: allow sending longer LP commandsAntonio Borneo1-8/+9
2020-09-07drm/bridge/synopsys: dsi: allow LP commands in video modeAntonio Borneo1-0/+8
2020-09-06drm/panel: s6e63m0: Fix up DRM_DEV* regressionLinus Walleij3-27/+17
2020-09-05drm/panel: s6e63m0: Order enable/disable sequenceLinus Walleij1-3/+15
2020-09-05drm/panel: s6e63m0: Add code to identify panelLinus Walleij1-0/+60
2020-09-05drm/panel: s6e63m0: Add reading functionalityLinus Walleij4-2/+43
2020-09-05drm/panel: s6e63m0: Add DSI transportLinus Walleij6-3/+144
2020-09-05drm/panel: s6e63m0: Break out SPI transportLinus Walleij5-70/+124
2020-09-03drm/managed: Cleanup of unused functions and polishing docsDaniel Vetter2-58/+22
2020-09-03drm/ttm: remove io_reserve_lru handling v3Christian König4-169/+24
2020-09-03drm/nouveau: move io_reserve_lru handling into the driver v5Christian König4-23/+127
2020-09-03drm/ttm: make sure that we always zero init mem.bus v2Christian König1-0/+9
2020-09-02drm/virtio: drop virtio_gpu_output->enabledGerd Hoffmann3-6/+1
2020-09-02drm/virtio: fix unblankGerd Hoffmann3-1/+15
2020-09-01drm/gma500: Constify static structsRikard Falkeborn1-3/+3