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path: root/drivers/gpu/drm
AgeCommit message (Expand)AuthorFilesLines
2019-04-05drm/i915: Use lockdep_pin_lock() over the construction of the requestChris Wilson2-0/+15
2019-04-04drm/i915: add Makefile magic for testing headers are self-containedJani Nikula11-68/+28
2019-04-04drm/i915: Fixup kerneldoc for intel_cdclk_needs_cd2x_updateChris Wilson1-0/+1
2019-04-04drm/i915: Be precise in types for i915_gem_busyChris Wilson1-9/+10
2019-04-04drm/i915: Update DRIVER_DATE to 20190404Joonas Lahtinen1-2/+2
2019-04-03drm/i915: Expose full 1024 LUT entries on ivb+Ville Syrjälä2-43/+34
2019-04-03drm/i915: Expose the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props on gen2/3Ville Syrjälä1-0/+5
2019-04-03drm/i915: Add "10.6" LUT mode for i965+Ville Syrjälä3-1/+71
2019-04-03drm/i915: Add 10bit LUT for ilk/snbVille Syrjälä3-10/+52
2019-04-03drm/i915: Implement split/10bit gamma for ivb/hswVille Syrjälä2-24/+95
2019-04-03drm/i915: Don't use split gamma when we don't have toVille Syrjälä2-95/+92
2019-04-03drm/i915: Extract ilk_lut_10()Ville Syrjälä1-16/+11
2019-04-03drm/i915: Skip modeset for cdclk changes if possibleVille Syrjälä4-34/+163
2019-04-03drm/i915: Remove redundant store of logical CDCLK stateImre Deak1-2/+0
2019-04-03drm/i915: Save the old CDCLK atomic stateImre Deak3-2/+23
2019-04-03drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabledVille Syrjälä5-23/+86
2019-04-03drm/i915: Move the decision to use the breadcrumb tasklet to the backendChris Wilson3-1/+10
2019-04-03drm/i915: Fix uninitialized mask in intel_device_info_subplatform_initTvrtko Ursulin1-1/+1
2019-04-03drm/i915: rename init/fini/prune uncore functionsDaniele Ceraolo Spurio3-10/+10
2019-04-03drm/i915: add intel_uncore_init_earlyDaniele Ceraolo Spurio3-1/+7
2019-04-02drm/i915/ehl: All EHL ports are combo physBob Paauwe1-1/+4
2019-04-02drm/i915: Only emit one semaphore per requestChris Wilson3-5/+15
2019-04-02drm/i915: Split out i915_priolist_types into its own headerChris Wilson5-30/+52
2019-04-02drm/i915: Move intel_engine_mask_t around for use by i915_request_types.hChris Wilson29-152/+191
2019-04-02drm/i915: Prefault before locking pages in shmem_pwriteChris Wilson1-6/+24
2019-04-01drm/i915: Introduce concept of a sub-platformTvrtko Ursulin6-42/+214
2019-04-01drm/i915: Remove redundant device id from IS_IRONLAKE_M macroTvrtko Ursulin1-2/+5
2019-04-01drm/i915: Split Pineview device info into desktop and mobileTvrtko Ursulin3-6/+12
2019-03-31drm/i915: Check domains for userptr on releaseChris Wilson3-5/+6
2019-03-31drm/i915: Avoid using ctx->file_priv during constructionChris Wilson1-9/+10
2019-03-30drm/i915/guc: Retry GuC load for all load failuresRobert M. Fosha1-1/+1
2019-03-29drm/i915: Always backoff after a drm_modeset_lock() deadlockChris Wilson1-1/+4
2019-03-29drm/i915: Program EXT2 GC MAX registersUma Shankar2-0/+23
2019-03-29drm/i915: Fix GCMAX color register programmingUma Shankar1-11/+11
2019-03-29drm/i915: fix i9xx irq enable/disableDaniele Ceraolo Spurio1-7/+3
2019-03-29drm/i915: move the edram detection out of uncore initDaniele Ceraolo Spurio5-52/+50
2019-03-28drm/i915: Skip the linear degamma LUT load on ICL+Ville Syrjälä1-27/+64
2019-03-28drm/i915: Drop the pointless linear legacy LUT load on CHVVille Syrjälä1-16/+1
2019-03-28drm/i915: Extract ilk_color_check()Ville Syrjälä1-43/+33
2019-03-28drm/i915: Extract bdw_color_check()Ville Syrjälä1-0/+39
2019-03-28drm/i915: Extract glk_color_check()Ville Syrjälä1-0/+40
2019-03-28drm/i915: Extract icl_color_check()Ville Syrjälä1-17/+53
2019-03-28drm/i915: Extract chv_color_check()Ville Syrjälä1-4/+36
2019-03-28drm/i915: Extract i9xx_color_check()Ville Syrjälä1-5/+28
2019-03-28drm/i915: Turn intel_color_check() into a vfuncVille Syrjälä2-10/+21
2019-03-28drm/i915: Extract check_luts()Ville Syrjälä1-28/+40
2019-03-28drm/i915: Update DRIVER_DATE to 20190328Joonas Lahtinen1-1/+1
2019-03-28drm/i915: Update DRIVER_DATE to 20190328Joonas Lahtinen1-1/+1
2019-03-28drm/i915: Update DRIVER_DATE to 20190328Joonas Lahtinen1-2/+2
2019-03-27drm/i915: Reject rotation for some hdr formatsMaarten Lankhorst1-0/+5
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