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path: root/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
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2022-11-09drm/nouveau/gr/gf117-: make ppc_nr[gpc] accurateBen Skeggs1-1/+1
We're going to be pulling in a chunk of code from NVGPU to fixup our SMID mappings on Volta and above, which depends on ppc_nr[gpc] reflecting the actual number of PPCs present, not the maximum number. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/gr/gf100-: move some init to init_exception2()Ben Skeggs1-0/+1
Ampere. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/gr/gf100-: move some init to init_rop_exceptions()Ben Skeggs1-0/+1
Ampere. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09drm/nouveau/gr/gf100-: move reset during golden ctx init to fecs_reset()Ben Skeggs1-0/+1
Ampere. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11drm/nouveau/gr: switch to instanced constructorBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
2020-01-15drm/nouveau/gr/gf100-: select implementation based on available FWBen Skeggs1-1/+8
This will allow for further customisation of the subdev depending on what firmware is available. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gp100-: use correct registers for zbc colour/depth setupBen Skeggs1-0/+1
These were missed the first time around due to the driver version I traced using the older registers still. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-gm10x: update register listsBen Skeggs1-0/+7
There are differences on GM200 and newer too, but we can't fix them there as they come from firmware packages. A request has been made to NVIDIA to release updated firmware. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: calculate and use sm mapping tableBen Skeggs1-0/+1
There's a number of places that require this data, so let's separate out the calculations to ensure they remain consistent. This is incorrect for GM200 and newer, but will produce the same results as we did before. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: port tile mapping calculations from NVGPUBen Skeggs1-0/+1
There's also a couple of hardcoded tables for a couple of very specific configurations that NVGPU's algorithm didn't work for. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: virtualise trap_mpBen Skeggs1-0/+1
Required to support Volta. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: delete duplicated init codeBen Skeggs1-77/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: virtualise init_400054Ben Skeggs1-1/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: apply be exception fixes from tracesBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: virtualise init_shader_exceptionsBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: virtualise init_tex_hww_esrBen Skeggs1-1/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: virtualise init_419eb4 + apply fixes from tracesBen Skeggs1-1/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: virtualise init_419cc0 + apply fixes from tracesBen Skeggs1-2/+2
Pulled some init out of main per-GPC/TPC loops to match RM. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: virtualise init_sked_hww_esrBen Skeggs1-1/+8
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: virtualise init_fecs_exceptions + apply fixes from tracesBen Skeggs1-3/+11
The value for GF100 has changed here, but it matches RM now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100: write 0x400124 during initBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: virtualise init_num_active_ltcsBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: virtualise init_zcullBen Skeggs1-29/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18drm/nouveau/gr/gf100-: virtualise init_vsc_stream_masterBen Skeggs1-1/+9
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-02-02drm/nouveau: Add support for BLCG on Kepler1Lyude Paul1-0/+207
This enables BLCG optimization for kepler1. When using clockgating, nvidia's firmware has a set of registers which are initially programmed by the vbios with various engine delays and other mysterious settings that are safe enough to bring up the GPU. However, the values used by the vbios are more power hungry then they need to be, so the nvidia driver writes it's own more optimized set of BLCG settings before enabling CG_CTRL. This adds support for programming the optimized BLCG values during engine/subdev init, which enables rather significant power savings. This introduces the nvkm_therm_clkgate_init() helper, which we use to program the optimized BLCG settings before enabling clockgating with nvkm_therm_clkgate_enable. As well, this commit shares a lot more code with Fermi since BLCG is mostly the same there as far as we can tell. In the future, it's likely we'll reformat the clkgate_packs for kepler1 so that they share a list of mmio packs with Fermi. Signed-off-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02drm/nouveau/gr/gf100-gk208: make use of init_gpc_mmu() hook to share setupBen Skeggs1-11/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20drm/nouveau/gr/gk104-: share implementation of ppc exception initBen Skeggs1-1/+18
This was really inconsistent, some implementations could touch PPCs that didn't exist, others neglected to touch ones that did. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20drm/nouveau/gr/gk104-: move rop_active_fbps init to nonctxBen Skeggs1-0/+12
Matches newer RM. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20drm/nouveau/fb/gf100-: allocate mmu debug buffersBen Skeggs1-2/+5
Later chipsets require setting this up both in FB and GR, so let's just move the allocation to FB. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20drm/nouveau/gr/gf100-: abstract fetching rop countBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20drm/nouveau/gr/gf100-: rename magic_not_rop_nr to screen_tile_row_offsetBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/gr: convert to new-style nvkm_engineBen Skeggs1-46/+21
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/pmu: convert to new-style nvkm_subdevBen Skeggs1-6/+3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/gr: convert user classes to new-style nvkm_objectBen Skeggs1-15/+13
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/gr: remove dependence on namedb/engctx lookupBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/gr: directly use instmem where currently possibleBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/gr: switch to device pri macrosBen Skeggs1-60/+61
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28drm/nouveau/gr: cosmetic changesBen Skeggs1-81/+81
This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-04-14drm/nouveau/gr/gf100-: add symbolic names for classesBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-04-14drm/nouveau/gr/gk104-gk20a: call pmu to disable any power-gating before ctor()Ben Skeggs1-1/+12
On some of these chipsets, reading NV_PGRAPH_GPC_GPM_PD_PES_TPC_ID_MASK can trigger a PRI fault and return an error code instead of a TPC mask, unless PGOB has been disabled first. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-22drm/nouveau/gr: namespace + nvidia gpu names (no binary change)Ben Skeggs1-0/+348
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-09 16:33:16 +0000