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path: root/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
AgeCommit message (Expand)AuthorFilesLines
2020-05-22drm/nouveau/disp/hda/gf119-: add HAL for programming device entry in SFBen Skeggs1-0/+1
2018-10-11drm/nouveau/disp: keep track of high-speed state, program into clockIlia Mirkin1-4/+7
2018-05-18drm/nouveau/disp/nv50-: fetch mask of available sors during oneinitBen Skeggs1-10/+9
2018-01-09drm/nouveau/disp/gf119: add missing drive vfunc ptrRob Clark1-0/+1
2017-06-17drm/nouveau/disp/nv50-: avoid creating ORs that aren't present on HWBen Skeggs1-1/+10
2017-06-16drm/nouveau/disp/nv50-: implement a common supervisor 2.2Ben Skeggs1-0/+33
2017-06-16drm/nouveau/disp: remove hw-specific customisation of output pathsBen Skeggs1-12/+0
2017-06-16drm/nouveau/disp/gf119-: port OR DP VCPI control to nvkm_iorBen Skeggs1-4/+4
2017-06-16drm/nouveau/disp/gt215-: port HDA ELD controls to nvkm_iorBen Skeggs1-0/+21
2017-06-16drm/nouveau/disp/g94-: port OR DP drive setting control to nvkm_iorBen Skeggs1-41/+11
2017-06-16drm/nouveau/disp/g94-: port OR DP training pattern control to nvkm_iorBen Skeggs1-6/+5
2017-06-16drm/nouveau/disp/g94-: port OR DP link power control to nvkm_iorBen Skeggs1-1/+1
2017-06-16drm/nouveau/disp/g94-: port OR DP link setup to nvkm_iorBen Skeggs1-9/+9
2017-06-16drm/nouveau/disp/g94-: port OR DP lane mapping to nvkm_iorBen Skeggs1-0/+3
2017-06-16drm/nouveau/disp/g84-: port OR HDMI control to nvkm_iorBen Skeggs1-0/+3
2017-06-16drm/nouveau/disp/nv50-: port OR power state control to nvkm_iorBen Skeggs1-0/+1
2017-06-16drm/nouveau/disp/nv50-: fetch head/OR state at beginning of supervisorBen Skeggs1-0/+24
2017-06-16drm/nouveau/disp: introduce input/output resource abstractionBen Skeggs1-0/+11
2017-06-16drm/nouveau/disp: shuffle functions aroundBen Skeggs1-37/+36
2016-11-07drm/nouveau/disp/sor/gf119-: add method to program mst payload informationBen Skeggs1-0/+12
2016-11-07drm/nouveau/disp/sor/gf119-: add method to control mst enableBen Skeggs1-1/+3
2016-07-06drm/nouveau/disp/sor/gf119: select correct sor when poking training patternBen Skeggs1-1/+2
2016-06-07drm/nouveau/disp/sor/gm107: training pattern registers are like gm200Ben Skeggs1-1/+1
2016-06-07drm/nouveau/disp/sor/gf119: both links use the same training registerBen Skeggs1-2/+1
2015-08-28drm/nouveau/disp: split user classes out from engine implementationsBen Skeggs1-0/+117
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